CYT4DNJBJS datasheet(16/209 Pages) INFINEON

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Datasheet

002-24601 Rev. *I

2023-02-14

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M7 dual

Functional description

3.3

Peripherals

3.3.1

Peripheral clock dividers

Integer and fractional clock dividers are provided for peripheral and timing purposes.

3.3.2

Peripheral protection unit

The peripheral protection unit (PPU) controls and monitors unauthorized access from all masters (CPU,

P-/M-DMA, Crypto, and any enabled debug interface) to the peripherals. It allows or restricts data transfers on the

bus infrastructure. The access rules are enforced based on specific properties of a transfer, such as an address

range for the transfer and access attributes (such as read/write, user/privilege, and secure/non-secure).

3.3.3

12-bit SAR ADC

CYT4DN contains one 1-Msps SAR ADC. This ADC can be clocked at up to 26.67 MHz and provide a 12-bit result in

26 clock cycles.

The references for the SAR ADC comes from a dedicated pair of inputs: VREFH and VREFL[11].

CYT4DN supports 32 logical ADC channels which can select one of 54 input sources. Sources include 48 external

inputs from I/Os, and six internal connections for diagnostic and monitoring purposes.

The number of ADC channels (per ADC and package type) are listed in Table 1-1.

SAR ADC has a sequencer, which autonomously cycles through the configured channels (sequencer scan) with

zero-switching overhead (that is, the aggregate sampling bandwidth, when clocked at 26.67 MHz, is equal to 1

Msps whether it is for a single channel or distributed over several channels). The sequencer switching is

controlled through a state machine or firmware. The sequencer prioritizes trigger requests, enables the

appropriate analog channel, controls ADC sampling, initiates ADC data conversion, manages results, and initiates

subsequent conversions for repetitive or group conversions without CPU intervention.

SAR ADC has two analog multiplexers used to connect the signals to be measured to the ADC. One is SARMUX0

which has 24 GPIO_STD inputs (ADC[0]_0 to ADC[0]_23), and six additional inputs to measure internal signals

such as a band-gap reference, a temperature sensor, VCCD, VDDA_ADC power supplies and AMUXBUSA/B signals.

The other multiplexer is SARMUX1 which has 24 GPIO_SMC inputs (ADC[1]_0 to ADC[1]_23).

CYT4DN has a temperature sensor. Software post processing is required to convert the temperature sensor

reading into kelvin or Celsius values.

To accommodate signals with varying source impedances and frequencies, it is possible to have different sample

times programmed for each channel. ADC also supports range comparison, which allows fast detection of

out-of-range values without having to wait for a sequencer scan to complete and for the CPU firmware to evaluate

the measurement for out-of-range values.

The ADC is not usable in DeepSleep and Hibernate modes as they require a high-speed clock. The ADC input

reference voltage VREFH range is 2.7 V to VDDA_ADC and VREFL is VSSA_ADC.

Table 3-2

Clock dividers - CPUSS Group (Number 0)

Divider Type

Instances

Description

div_8

Integer divider, 8 bits

div_16

Integer divider, 16 bits

div_16_5

Fractional divider, 16.5 bits (16 integer bits, 5 fractional bits)

div_24_5

Fractional divider, 24.5 bits (24 integer bits, 5 fractional bits)

Table 3-3

Clock dividers - CPUSS Group (Number 1)

Divider Type

Instances

Description

div_8

Integer divider, 8 bits

div_16

Integer divider, 16 bits

div_24_5

Fractional divider, 24.5 bits (24 integer bits, 5 fractional bits)

Note

11.VREF_L prevents IR drops in the VSSIO and VSSA_ADC paths from impacting the measurements. VREF_L, when properly connected,

reduces or removes the impact of IR drops in the VSS and VSSA_ADC paths from measurements.

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