CYT4DNJBJS datasheet(17/209 Pages) INFINEON

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Datasheet

002-24601 Rev. *I

2023-02-14

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M7 dual

Functional description

3.3.4

Timer/counter/PWM block (TCPWM)

The TCPWM block consists of 16-bit (50 channels) and 32-bit (32 channels) counters with user-programmable

period.

Each TCPWM counter contains a capture register to record the count at the time of an event, a period register

(used to either stop or auto-reload the counter when its count is equal to the period register), and compare

registers to generate signals that are used as PWM duty-cycle outputs.

Each counter within the TCPWM block supports several functional modes such as timer, capture, quadrature,

PWM, PWM with dead-time insertion (PWM_DT, 8-bit), pseudo-random PWM (PWM_PR), and shift-register.

The TCPWM block also provides true and complement outputs, with programmable offset between them, to

allow their use as deadband complementary PWM outputs. The TCPWM block also has a kill input (only for the

PWM mode) to force outputs to a predetermined state; for example, this may be used in motor-drive systems

when an overcurrent state is detected and the PWMs driving the FETs need to be shut off immediately (no time

for software intervention).

Twelve of the 16-bit counters are optimized for DC and stepper motor-control operations, these also have ZPD

(Zero Point detection) and slew rate control capabilities. Two of these TCPWM channels constitute one SMC

channel.

3.3.5

Serial Communication Blocks (SCB)

CYT4DN contains up to 12 serial communication blocks, each configurable to support I2C, UART, or SPI.

3.3.5.1

I2C interface

An SCB can be configured to implement a full I2C master (capable of multi-master arbitration) or slave interface.

Each SCB configured for I2C can operate at speeds of up to 1 Mbps (Fast-mode Plus) and has flexible buffering

options to reduce the interrupt overhead and latency of the CPU. In addition, each SCB supports FIFO buffering

for receive and transmit data, which, by increasing the time for the CPU to read the data, reduces the need for

clock stretching. The I2C interface is compatible with Standard, Fast-mode, and Fast-mode Plus devices as

specified in the NXP I2C-bus specification and user manual (UM10204). The I2C-bus I/O is implemented with GPIO

in open-drain modes[12, 13].

3.3.5.2

UART interface

When configured as a UART, each SCB provides a full-featured UART with maximum signaling rate determined

by the configured peripheral-clock frequency and over-sampling rate. It supports infrared interface (IrDA) and

SmartCard (ISO 7816) protocols, which are minor variants of the UART protocol. It also supports the 9-bit multi-

processor mode that allows the addressing of peripherals connected over common Rx and Tx lines. Common

UART functions such as parity, number of stop bits, break detect, and frame error are supported. FIFO buffering

of transmit and receive data allows greater CPU service latencies to be tolerated.

The LIN protocol is supported by the UART. LIN is based on a single-master multi-slave topology. There is one

master node and multiple slave nodes on the LIN bus. The SCB UART supports only LIN slave functionality.

Compared to the dedicated LIN blocks, an SCB/UART used for LIN requires a higher level of software interaction

and increased CPU load.

Notes

12.This is not 100% compliant with the I2C-bus specification; I/Os are not over-voltage tolerant, do not support the 20-mA sink

requirement of Fast-mode Plus, and violate the leakage specification when no power is applied.

13.See Table 26-10 'Serial Communication Block (SCB) specifications' for supported IO-cells and I2C modes.

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