CYT4DNJBJS datasheet(92/209 Pages) INFINEON

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Datasheet

002-24601 Rev. *I

2023-02-14

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M7 dual

Miscellaneous configuration

Table 24-1

Miscellaneous configuration for CYT4DN devices

Sl. No.

Configuration

Number/

Instances

Description

SRSS_NUM_CLKPATH

Number of clock paths. One for each of FLL, PLL, Direct and

CSV

SRSS_NUM_HFROOT

Number of CLK_HFs present

PERI_PC_NR

Number of protection contexts

PERI_PERI_PCLK_PCLK_GROUP_NR

Number of asynchronous PCLK groups

PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_8_VECT

Group 0, Number of divide-by-8 clock dividers

PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_VECT

Group 0, Number of divide-by-16 clock dividers

PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_5_VECT

Group 0, Number of divide-by-16.5 clock dividers

PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_24_5_VECT

Group 0, Number of divide-by-24.5 clock dividers

PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_CLOCK_VECT

Group 0, Number of programmable clocks [1, 256]

PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_8_VECT

Group 1, Number of divide-by-8 clock dividers

PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_VECT

Group 1, Number of divide-by-16 clock dividers

PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_24_5_VECT

Group 1, Number of divide-by-24.5 clock dividers

PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_CLOCK_VECT

Group 1, Number of programmable clocks [1, 256]

CPUSS_CM0P_MPU_NR

Number of MPU regions in CM0+

CPUSS_CM7_0_FPU_LVL

CM7_0 Floating point unit configuration.

0 - No FPU

1 - Single precision FPU

2 - Single and Double precision FPU

CPUSS_CM7_0_MPU_NR

Number of MPU regions in CM7_0

CPUSS_CM7_0_ICACHE_SIZE

CM7_0 Instruction cache (ICACHE) size in KB

CPUSS_CM7_0_DCACHE_SIZE

CM7_0 Data cache size (DCACHE) in KB

CPUSS_CM7_0_ITCM_SIZE

CM7_0 Instruction TCM (ITCM) size in KB

CPUSS_CM7_0_DTCM_SIZE

CM7_0 Data TCM (DTCM) size in KB

CPUSS_CM7_1_FPU_LVL

CM7_1 Floating point unit configuration.

0 - No FPU

1 - Single precision FPU

2 - Single and Double precision FPU

CPUSS_CM7_1_MPU_NR

Number of MPU regions in CM7_1

CPUSS_CM7_1_ICACHE_SIZE

CM7_1 Instruction cache (ICACHE) size in KB

CPUSS_CM7_1_DCACHE_SIZE

CM7_1 Data cache size (DCACHE) in KB

CPUSS_CM7_1_ITCM_SIZE

CM7_1 Instruction TCM (ITCM) size in KB

CPUSS_CM7_1_DTCM_SIZE

CM7_1 Data TCM (DTCM) size in KB

CPUSS_DW0_CH_NR

Number of P-DMA0 channels

CPUSS_DW1_CH_NR

Number of P-DMA1 channels

CPUSS_DMAC_CH_NR

Number of M-DMA0 controller channels

CPUSS_CRYPTO_BUFF_SIZE

2048

Number of 32-bit words in the IP internal memory buffer

(to allow for a 256-B, 512-B, 1-KB, 2-KB, 4-KB, 8-KB, 16-KB,

and 32-KB memory buffer)

CPUSS_FAULT_FAULT_NR

Number of fault structures

CPUSS_IPC_IPC_NR

Number of IPC structures

0 - Reserved for CM0+ access

1 - Reserved for CM7_0 access

2 - Reserved for CM7_1 access

3 - Reserved for DAP access

Remaining for user purposes

CPUSS_PROT_SMPU_STRUCT_NR

Number of SMPU protection structures

SCB0_EZ_DATA_NR

256

Number of EZ memory bytes. This memory is used in EZ

mode, CMD_RESP mode and FIFO mode.

Note: Only SCB0 supports EZ mode

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