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CYT4DNJBJS датащи(PDF) 48 Page - Infineon Technologies AG

номер детали CYT4DNJBJS
подробное описание детали  TRAVEO™ T2G 32-bit Automotive MCU Based on Arm® Cortex®-M7 dual
PDF  209 Pages
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производитель  INFINEON [Infineon Technologies AG]
домашняя страница  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

CYT4DNJBJS датащи(HTML) 48 Page - Infineon Technologies AG

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Datasheet
48
002-24601 Rev. *I
2023-02-14
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Interrupts and wake-up assignments
14
Interruptsand wake-up assignments
Table 14-1
Peripheral interrupt assignments and wake-up sources
Interrupt
Source
Power
mode
Description
0
cpuss_interrupts_ipc_0_IRQn
DeepSleep CPUSS Inter Process Communication Interrupt #0
1
cpuss_interrupts_ipc_1_IRQn
DeepSleep CPUSS Inter Process Communication Interrupt #1
2
cpuss_interrupts_ipc_2_IRQn
DeepSleep CPUSS Inter Process Communication Interrupt #2
3
cpuss_interrupts_ipc_3_IRQn
DeepSleep CPUSS Inter Process Communication Interrupt #3
4
cpuss_interrupts_ipc_4_IRQn
DeepSleep CPUSS Inter Process Communication Interrupt #4
5
cpuss_interrupts_ipc_5_IRQn
DeepSleep CPUSS Inter Process Communication Interrupt #5
6
cpuss_interrupts_ipc_6_IRQn
DeepSleep CPUSS Inter Process Communication Interrupt #6
7
cpuss_interrupts_ipc_7_IRQn
DeepSleep CPUSS Inter Process Communication Interrupt #7
8
cpuss_interrupts_fault_0_IRQn
DeepSleep CPUSS Fault Structure #0 Interrupt
9
cpuss_interrupts_fault_1_IRQn
DeepSleep CPUSS Fault Structure #1 Interrupt
10
cpuss_interrupts_fault_2_IRQn
DeepSleep CPUSS Fault Structure #2 Interrupt
11
cpuss_interrupts_fault_3_IRQn
DeepSleep CPUSS Fault Structure #3 Interrupt
12
srss_interrupt_backup_IRQn
DeepSleep BACKUP domain Interrupt
13
srss_interrupt_mcwdt_0_IRQn
DeepSleep Multi Counter Watchdog Timer#0 interrupt
14
srss_interrupt_mcwdt_1_IRQn
DeepSleep Multi Counter Watchdog Timer#1 interrupt
15
srss_interrupt_mcwdt_2_IRQn
DeepSleep Multi Counter Watchdog Timer#2 interrupt
17
srss_interrupt_wdt_IRQn
DeepSleep Hardware Watchdog Timer interrupt
18
srss_interrupt_IRQn
DeepSleep Other combined Interrupts for SRSS (LVD, CLKCAL)
19
evtgen_0_interrupt_dpslp_IRQn
DeepSleep Event gen DeepSleep domain interrupt
20
scb_0_interrupt_IRQn
DeepSleep SCB0 interrupt (DeepSleep capable)
22
ioss_interrupt_vdd_IRQn
DeepSleep I/O Supply (VDDIO, VDDA_ADC, VDDD) state change
Interrupt
23
ioss_interrupt_gpio_dpslp_IRQn
DeepSleep Consolidated Interrupt for GPIO*, All Ports
24
ioss_interrupts_gpio_dpslp_0_IRQn
DeepSleep GPIO_ENH Port #0 Interrupt
25
ioss_interrupts_gpio_dpslp_1_IRQn
DeepSleep GPIO_STD Port #1 Interrupt
26
ioss_interrupts_gpio_dpslp_2_IRQn
DeepSleep GPIO_STD Port #2 Interrupt
27
ioss_interrupts_gpio_dpslp_3_IRQn
DeepSleep GPIO_STD Port #3 Interrupt
28
ioss_interrupts_gpio_dpslp_4_IRQn
DeepSleep GPIO_STD Port #4 Interrupt
29
ioss_interrupts_gpio_dpslp_5_IRQn
DeepSleep GPIO_STD Port #5 Interrupt
30
ioss_interrupts_gpio_dpslp_6_IRQn
DeepSleep GPIO_STD Port #6 Interrupt
31
ioss_interrupts_gpio_dpslp_7_IRQn
DeepSleep GPIO_STD Port #7 Interrupt
32
ioss_interrupts_gpio_dpslp_8_IRQn
DeepSleep GPIO_STD Port #8 Interrupt
33
ioss_interrupts_gpio_dpslp_9_IRQn
DeepSleep GPIO_SMC Port #9 Interrupt
35
ioss_interrupts_gpio_dpslp_11_IRQn
DeepSleep GPIO_SMC Port #11 Interrupt
36
ioss_interrupts_gpio_dpslp_12_IRQn
DeepSleep GPIO_SMC Port #12 Interrupt
37
ioss_interrupts_gpio_dpslp_29_IRQn
DeepSleep GPIO_ENH Port #29 Interrupt
50
ioss_interrupt_gpio_act_IRQn
Active
Consolidated Interrupt for HSIO*, All Ports
53
ioss_interrupts_gpio_act_13_IRQn
Active
HSIO_STD Port Interrupt #13 Interrupt
54
ioss_interrupts_gpio_act_14_IRQn
Active
HSIO_STD Port Interrupt #14 Interrupt
55
ioss_interrupts_gpio_act_15_IRQn
Active
HSIO_STD_LN Port Interrupt #15 Interrupt
56
ioss_interrupts_gpio_act_16_IRQn
Active
HSIO_STD_LN Port Interrupt #16 Interrupt



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