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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CYT4DNJBJS датащи(PDF) 46 Page - Infineon Technologies AG |
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CYT4DNJBJS датащи(HTML) 46 Page - Infineon Technologies AG |
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46 / 209 page  Datasheet 46 002-24601 Rev. *I 2023-02-14 TRAVEO™ T2G 32-bit Automotive MCU Based on Arm® Cortex®-M7 dual Alternate function pin assignments 39 ETHx_TXD_y Ethernet Ethernet transmit data line, x-ETH module number, y-transmit channel number 40 ETHx_RXD_y Ethernet Ethernet receive data line, x-ETH module number, y-receive channel number 41 ETHx_RX_CTL Ethernet Ethernet receive control line, x-ETH module number 42 ETHx_RX_CLK Ethernet Ethernet receive clock line, x-ETH module number 43 CAL_SUP_NZ System ETAS Calibration support line 44 FAULT_OUT_x SRSS Fault output line x-0 to 3 45 TRACE_DATA_x SRSS Trace data-out line x-0 to 3 46 TRACE_CLOCK SRSS Trace clock line 47 RTC_CAL SRSS RTC RTC calibration clock input 48 SWJ_TRSTN SRSS JTAG Test reset line (Active low) 49 SWJ_SWO_TDO SRSS JTAG Test data output/SWO (Serial Wire Output) 50 SWJ_SWCLK_TCLK SRSS JTAG Test clock/SWD clock (Serial Wire Clock) 51 SWJ_SWDIO_TMS SRSS JTAG Test mode select/SWD data (Serial Wire Data Input/Output) 52 SWJ_SWDOE_TDI SRSS JTAG Test data input 53 HIBERNATE_WAKEUP[x] SRSS Hibernate wakeup line x-0 to N (Check Table 11-1) 54 EXT_CLK SRSS External clock input 55 IO_CLK_HF[5] SRSS CLK_HF5 clock output 56 PMIC_EN SRSS PMIC PMIC control line, Enable output for PMIC 57 PMIC_STATUS SRSS PMIC PMIC status line, Power good input from PMIC 58 ADC[x]_y PASS SAR SAR, channel, x-SAR number, y-channel number 59 ADC[x]_M PASS SAR SAR motor control input, x-SAR number 60 EXT_MUX[x]_y PASS SAR External SAR MUX inputs, x-MUX number, y-MUX input 0 to 2 61 EXT_MUX[x]_EN PASS SAR External SAR MUX enable line 62 PWM_LINEx_N[y] PCMPWM Audio PWM complementary output line, x-PWM module instance 63 PWM_LINEx_P[y] PCMPWM Audio PWM output line, x-PWM module instance 64 PWM_MCK[x] PCMPWM Audio PWM master clock input, x-PWM module instance 65 SG_AMPL[x] SG Sound generator (SG) amplitude output, x-SG module number 66 SG_MCK[x] SG Sound generator (SG) master clock input, x-SG module number 67 SG_TONE[x] SG Sound generator (SG) tone output, x-SG module number 68 TDM_RX_FSYNC[x] TDM TDM receive frame sync, x-TDM module number 69 TDM_RX_MCK[x] TDM TDM receive master clock input, x-TDM module number 70 TDM_RX_SCK[x] TDM TDM receive bit clock, x-TDM module number 71 TDM_RX_SD[x] TDM TDM receive serial data, x-TDM module number 72 TDM_TX_FSYNC[x] TDM TDM transmit frame sync, x-TDM module number 73 TDM_TX_MCK[x] TDM TDM transmit master clock input, x-TDM module number 74 TDM_TX_SCK[x] TDM TDM transmit bit clock, x-TDM module number 75 TDM_TX_SD[x] TDM TDM transmit serial data, x-TDM module number 76 TTL_CAPx_CLK VIDEOSS Capture clock, x-capture module number 77 TTL_CAPx_DATA[y] VIDEOSS Capture data lines, x-capture module number, y- (0-26) data line 78 TTL_DSPx_CONTROL[y] VIDEOSS Display control line, x-display number, y-0/lvalid, 1/vertical sync signal, 2/display enable (DE) 79 TTL_DSPx_CLOCK VIDEOSS Display clock line (PCLK), x-display number 80 TTL_DSPx_DATA_A0[y] VIDEOSS Display data (A0/1 used in pairs), x-display number, y- (0-11) color data 81 TTL_DSPx_DATA_A1[y] VIDEOSS Display data (A0/1 used in pairs), x-display number, y- (0-11) color data 82 DAC_MCK AUDIODAC DAC external master clock input 83 DAC_AOUTS_x AUDIODAC DAC output signal, x-left (L) or right (R) signal Table 13-2 Pin function description (continued) Sl. No. Pin Module Description |
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