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CYT4DNJBJS датащи(PDF) 79 Page - Infineon Technologies AG

номер детали CYT4DNJBJS
подробное описание детали  TRAVEO™ T2G 32-bit Automotive MCU Based on Arm® Cortex®-M7 dual
PDF  209 Pages
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производитель  INFINEON [Infineon Technologies AG]
домашняя страница  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

CYT4DNJBJS датащи(HTML) 79 Page - Infineon Technologies AG

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Datasheet
79
002-24601 Rev. *I
2023-02-14
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Peripheral protection unit fixed structure pairs
128
DW0_CH_STRUCT32_CH
0x40288800
0x00000040 P-DMA#0 Channel #32
129
DW0_CH_STRUCT33_CH
0x40288840
0x00000040 P-DMA#0 Channel #33
130
DW0_CH_STRUCT34_CH
0x40288880
0x00000040 P-DMA#0 Channel #34
131
DW0_CH_STRUCT35_CH
0x402888C0
0x00000040 P-DMA#0 Channel #35
132
DW0_CH_STRUCT36_CH
0x40288900
0x00000040 P-DMA#0 Channel #36
133
DW0_CH_STRUCT37_CH
0x40288940
0x00000040 P-DMA#0 Channel #37
134
DW0_CH_STRUCT38_CH
0x40288980
0x00000040 P-DMA#0 Channel #38
135
DW0_CH_STRUCT39_CH
0x402889C0
0x00000040 P-DMA#0 Channel #39
136
DW0_CH_STRUCT40_CH
0x40288A00
0x00000040 P-DMA#0 Channel #40
137
DW0_CH_STRUCT41_CH
0x40288A40
0x00000040 P-DMA#0 Channel #41
138
DW0_CH_STRUCT42_CH
0x40288A80
0x00000040 P-DMA#0 Channel #42
139
DW0_CH_STRUCT43_CH
0x40288AC0
0x00000040 P-DMA#0 Channel #43
140
DW0_CH_STRUCT44_CH
0x40288B00
0x00000040 P-DMA#0 Channel #44
141
DW0_CH_STRUCT45_CH
0x40288B40
0x00000040 P-DMA#0 Channel #45
142
DW0_CH_STRUCT46_CH
0x40288B80
0x00000040 P-DMA#0 Channel #46
143
DW0_CH_STRUCT47_CH
0x40288BC0
0x00000040 P-DMA#0 Channel #47
144
DW0_CH_STRUCT48_CH
0x40288C00
0x00000040 P-DMA#0 Channel #48
145
DW0_CH_STRUCT49_CH
0x40288C40
0x00000040 P-DMA#0 Channel #49
146
DW0_CH_STRUCT50_CH
0x40288C80
0x00000040 P-DMA#0 Channel #50
147
DW0_CH_STRUCT51_CH
0x40288CC0
0x00000040 P-DMA#0 Channel #51
148
DW0_CH_STRUCT52_CH
0x40288D00
0x00000040 P-DMA#0 Channel #52
149
DW0_CH_STRUCT53_CH
0x40288D40
0x00000040 P-DMA#0 Channel #53
150
DW0_CH_STRUCT54_CH
0x40288D80
0x00000040 P-DMA#0 Channel #54
151
DW0_CH_STRUCT55_CH
0x40288DC0
0x00000040 P-DMA#0 Channel #55
152
DW0_CH_STRUCT56_CH
0x40288E00
0x00000040 P-DMA#0 Channel #56
153
DW0_CH_STRUCT57_CH
0x40288E40
0x00000040 P-DMA#0 Channel #57
154
DW0_CH_STRUCT58_CH
0x40288E80
0x00000040 P-DMA#0 Channel #58
155
DW0_CH_STRUCT59_CH
0x40288EC0
0x00000040 P-DMA#0 Channel #59
156
DW0_CH_STRUCT60_CH
0x40288F00
0x00000040 P-DMA#0 Channel #60
157
DW0_CH_STRUCT61_CH
0x40288F40
0x00000040 P-DMA#0 Channel #61
158
DW0_CH_STRUCT62_CH
0x40288F80
0x00000040 P-DMA#0 Channel #62
159
DW0_CH_STRUCT63_CH
0x40288FC0
0x00000040 P-DMA#0 Channel #63
160
DW0_CH_STRUCT64_CH
0x40289000
0x00000040 P-DMA#0 Channel #64
161
DW0_CH_STRUCT65_CH
0x40289040
0x00000040 P-DMA#0 Channel #65
162
DW0_CH_STRUCT66_CH
0x40289080
0x00000040 P-DMA#0 Channel #66
163
DW0_CH_STRUCT67_CH
0x402890C0
0x00000040 P-DMA#0 Channel #67
164
DW0_CH_STRUCT68_CH
0x40289100
0x00000040 P-DMA#0 Channel #68
165
DW0_CH_STRUCT69_CH
0x40289140
0x00000040 P-DMA#0 Channel #69
166
DW0_CH_STRUCT70_CH
0x40289180
0x00000040 P-DMA#0 Channel #70
167
DW0_CH_STRUCT71_CH
0x402891C0
0x00000040 P-DMA#0 Channel #71
168
DW0_CH_STRUCT72_CH
0x40289200
0x00000040 P-DMA#0 Channel #72
169
DW0_CH_STRUCT73_CH
0x40289240
0x00000040 P-DMA#0 Channel #73
170
DW0_CH_STRUCT74_CH
0x40289280
0x00000040 P-DMA#0 Channel #74
171
DW0_CH_STRUCT75_CH
0x402892C0
0x00000040 P-DMA#0 Channel #75
172
DW1_CH_STRUCT0_CH
0x40298000
0x00000040 P-DMA#1 Channel #0
Table 22-1
PPU fixed structure pairs (continued)
Pair
No.
PPU Fixed Structure Pair
Address
Size
Description



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