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CYT4DNJBJS датащи(PDF) 52 Page - Infineon Technologies AG

номер детали CYT4DNJBJS
подробное описание детали  TRAVEO™ T2G 32-bit Automotive MCU Based on Arm® Cortex®-M7 dual
PDF  209 Pages
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производитель  INFINEON [Infineon Technologies AG]
домашняя страница  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

CYT4DNJBJS датащи(HTML) 52 Page - Infineon Technologies AG

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Datasheet
52
002-24601 Rev. *I
2023-02-14
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Interrupts and wake-up assignments
318
cpuss_interrupts_dw0_22_IRQn
Active
CPUSS P-DMA0, Channel #22 Interrupt
319
cpuss_interrupts_dw0_23_IRQn
Active
CPUSS P-DMA0, Channel #23 Interrupt
320
cpuss_interrupts_dw0_24_IRQn
Active
CPUSS P-DMA0, Channel #24 Interrupt
321
cpuss_interrupts_dw0_25_IRQn
Active
CPUSS P-DMA0, Channel #25 Interrupt
322
cpuss_interrupts_dw0_26_IRQn
Active
CPUSS P-DMA0, Channel #26 Interrupt
323
cpuss_interrupts_dw0_27_IRQn
Active
CPUSS P-DMA0, Channel #27 Interrupt
324
cpuss_interrupts_dw0_28_IRQn
Active
CPUSS P-DMA0, Channel #28 Interrupt
325
cpuss_interrupts_dw0_29_IRQn
Active
CPUSS P-DMA0, Channel #29 Interrupt
326
cpuss_interrupts_dw0_30_IRQn
Active
CPUSS P-DMA0, Channel #30 Interrupt
327
cpuss_interrupts_dw0_31_IRQn
Active
CPUSS P-DMA0, Channel #31 Interrupt
328
cpuss_interrupts_dw0_32_IRQn
Active
CPUSS P-DMA0, Channel #32 Interrupt
329
cpuss_interrupts_dw0_33_IRQn
Active
CPUSS P-DMA0, Channel #33 Interrupt
330
cpuss_interrupts_dw0_34_IRQn
Active
CPUSS P-DMA0, Channel #34 Interrupt
331
cpuss_interrupts_dw0_35_IRQn
Active
CPUSS P-DMA0, Channel #35 Interrupt
332
cpuss_interrupts_dw0_36_IRQn
Active
CPUSS P-DMA0, Channel #36 Interrupt
333
cpuss_interrupts_dw0_37_IRQn
Active
CPUSS P-DMA0, Channel #37 Interrupt
334
cpuss_interrupts_dw0_38_IRQn
Active
CPUSS P-DMA0, Channel #38 Interrupt
335
cpuss_interrupts_dw0_39_IRQn
Active
CPUSS P-DMA0, Channel #39 Interrupt
336
cpuss_interrupts_dw0_40_IRQn
Active
CPUSS P-DMA0, Channel #40 Interrupt
337
cpuss_interrupts_dw0_41_IRQn
Active
CPUSS P-DMA0, Channel #41 Interrupt
338
cpuss_interrupts_dw0_42_IRQn
Active
CPUSS P-DMA0, Channel #42 Interrupt
339
cpuss_interrupts_dw0_43_IRQn
Active
CPUSS P-DMA0, Channel #43 Interrupt
340
cpuss_interrupts_dw0_44_IRQn
Active
CPUSS P-DMA0, Channel #44 Interrupt
341
cpuss_interrupts_dw0_45_IRQn
Active
CPUSS P-DMA0, Channel #45 Interrupt
342
cpuss_interrupts_dw0_46_IRQn
Active
CPUSS P-DMA0, Channel #46 Interrupt
343
cpuss_interrupts_dw0_47_IRQn
Active
CPUSS P-DMA0, Channel #47 Interrupt
344
cpuss_interrupts_dw0_48_IRQn
Active
CPUSS P-DMA0, Channel #48 Interrupt
345
cpuss_interrupts_dw0_49_IRQn
Active
CPUSS P-DMA0, Channel #49 Interrupt
346
cpuss_interrupts_dw0_50_IRQn
Active
CPUSS P-DMA0, Channel #50 Interrupt
347
cpuss_interrupts_dw0_51_IRQn
Active
CPUSS P-DMA0, Channel #51 Interrupt
348
cpuss_interrupts_dw0_52_IRQn
Active
CPUSS P-DMA0, Channel #52 Interrupt
349
cpuss_interrupts_dw0_53_IRQn
Active
CPUSS P-DMA0, Channel #53 Interrupt
350
cpuss_interrupts_dw0_54_IRQn
Active
CPUSS P-DMA0, Channel #54 Interrupt
351
cpuss_interrupts_dw0_55_IRQn
Active
CPUSS P-DMA0, Channel #55 Interrupt
352
cpuss_interrupts_dw0_56_IRQn
Active
CPUSS P-DMA0, Channel #56 Interrupt
353
cpuss_interrupts_dw0_57_IRQn
Active
CPUSS P-DMA0, Channel #57 Interrupt
354
cpuss_interrupts_dw0_58_IRQn
Active
CPUSS P-DMA0, Channel #58 Interrupt
355
cpuss_interrupts_dw0_59_IRQn
Active
CPUSS P-DMA0, Channel #59 Interrupt
356
cpuss_interrupts_dw0_60_IRQn
Active
CPUSS P-DMA0, Channel #60 Interrupt
357
cpuss_interrupts_dw0_61_IRQn
Active
CPUSS P-DMA0, Channel #61 Interrupt
358
cpuss_interrupts_dw0_62_IRQn
Active
CPUSS P-DMA0, Channel #62 Interrupt
359
cpuss_interrupts_dw0_63_IRQn
Active
CPUSS P-DMA0, Channel #63 Interrupt
360
cpuss_interrupts_dw0_64_IRQn
Active
CPUSS P-DMA0, Channel #64 Interrupt
Table 14-1
Peripheral interrupt assignments and wake-up sources (continued)
Interrupt
Source
Power
mode
Description



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