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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CYT4DNJBJS датащи(PDF) 68 Page - Infineon Technologies AG |
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CYT4DNJBJS датащи(HTML) 68 Page - Infineon Technologies AG |
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68 / 209 page  Datasheet 68 002-24601 Rev. *I 2023-02-14 TRAVEO™ T2G 32-bit Automotive MCU Based on Arm® Cortex®-M7 dual Triggers one-to-one 22 PASS0_CH_RANGEVIO_TR_OUT[22] TCPWM0_16M_ONE_CNT_TR_IN[2] SAR0 ch#22, range violation to TCPWM0 Group#1 Counter#02 trig=0 23 PASS0_CH_RANGEVIO_TR_OUT[23] TCPWM0_16M_ONE_CNT_TR_IN[3] SAR0 ch#23, range violation to TCPWM0 Group#1 Counter#03 trig=0 24 PASS0_CH_RANGEVIO_TR_OUT[24] TCPWM0_16M_ONE_CNT_TR_IN[4] SAR0 ch#24, range violation to TCPWM0 Group#1 Counter#04 trig=0 25 PASS0_CH_RANGEVIO_TR_OUT[25] TCPWM0_16M_ONE_CNT_TR_IN[5] SAR0 ch#25, range violation to TCPWM0 Group#1 Counter#05 trig=0 26 PASS0_CH_RANGEVIO_TR_OUT[26] TCPWM0_16M_ONE_CNT_TR_IN[6] SAR0 ch#26, range violation to TCPWM0 Group#1 Counter#06 trig=0 27 PASS0_CH_RANGEVIO_TR_OUT[27] TCPWM0_16M_ONE_CNT_TR_IN[7] SAR0 ch#27, range violation to TCPWM0 Group#1 Counter#07 trig=0 28 PASS0_CH_RANGEVIO_TR_OUT[28] TCPWM0_16M_ONE_CNT_TR_IN[8] SAR0 ch#28, range violation to TCPWM0 Group#1 Counter#08 trig=0 29 PASS0_CH_RANGEVIO_TR_OUT[29] TCPWM0_16M_ONE_CNT_TR_IN[9] SAR0 ch#29, range violation to TCPWM0 Group#1 Counter#09 trig=0 30 PASS0_CH_RANGEVIO_TR_OUT[30] TCPWM0_16M_ONE_CNT_TR_IN[10] SAR0 ch#30, range violation to TCPWM0 Group#1 Counter#10 trig=0 31 PASS0_CH_RANGEVIO_TR_OUT[31] TCPWM0_16M_ONE_CNT_TR_IN[11] SAR0 ch#31, range violation to TCPWM0 Group#1 Counter#11 trig=0 MUX Group 3: TCPWM0 to PASS SARx 0:19 TCPWM0_16_TR_OUT1[0:19] PASS0_CH_TR_IN[0:19] TCPWM0 Group #0 Counter #00 through 19 (PWM0_0 to PWM0_19) to SAR0 ch#0 through SAR0 ch#19 20:31 TCPWM0_16M_TR_OUT1[0:11] PASS0_CH_TR_IN[20:31] TCPWM0 Group #1 Counter #00 through 11 (PWM0_M_0 to PWM0_M_11) to SAR0 ch#20 through SAR0 ch#31 MUX Group 4: Acknowledge triggers from P-DMA1 to CAN1 0 PDMA1_TR_OUT[40] CAN1_DBG_TR_ACK[0] CAN1 Channel#0 P-DMA1 acknowledge 1 PDMA1_TR_OUT[43] CAN1_DBG_TR_ACK[1] CAN1 Channel#1 P-DMA1 acknowledge MUX Group 5: Acknowledge triggers from P-DMA0 to CAN0 0 PDMA0_TR_OUT[32] CAN0_DBG_TR_ACK[0] CAN0 Channel#0 P-DMA0 acknowledge 1 PDMA0_TR_OUT[35] CAN0_DBG_TR_ACK[1] CAN0 Channel#1 P-DMA0 acknowledge MUX Group 6: TCPWM0 to LIN0 triggers 0:1 TCPWM0_16_TR_OUT1[24:25] LIN0_CMD_TR_IN[0:1] TCPWM0 (Group #0 Counter #24 to #25) to LIN0 MUX Group 7: TCPWM0_TO_CXPI (TCPWM0 to CXPI) 0:1 TCPWM0_16_TR_OUT1[26:27] CXPI0_CMD_TR_IN[0:1] TCPWM0 (Group #0 Counter #24 to #25) to CXPI0 Table 19-1 Triggers 1:1 (continued) Input Trigger In Trigger Out Description |
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