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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CYT4DNJBJS датащи(PDF) 10 Page - Infineon Technologies AG |
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CYT4DNJBJS датащи(HTML) 10 Page - Infineon Technologies AG |
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10 / 209 page  Datasheet 10 002-24601 Rev. *I 2023-02-14 TRAVEO™ T2G 32-bit Automotive MCU Based on Arm® Cortex®-M7 dual Blocks and functionality 2Blocks and functionality Block diagram The Block diagram shows a simplified view of the interconnection between subsystems and blocks. CYT4DN has five major subsystems: CPU, system resources, peripherals, graphics, and I/O[4,5,6,7,8]. The color-coding shows the lowest power mode where the particular block is still functional. CYT4DN provides extensive support for programming, testing, debugging, and tracing of both hardware and firmware. Debug-on-chip functionality enables in-system debugging using the production device. It does not require special interfaces, debugging pods, simulators, or emulators. The JTAG interface is fully compatible with industry-standard third-party probes such as I-jet, J-Link, and GHS. The debug circuits are enabled by default. CYT4DN provides a high level of security with robust flash protection and the ability to disable features such as debug. Additionally, each device interface can be permanently disabled for applications concerned with phishing attacks due to a maliciously reprogrammed device or attempts to defeat security by starting and interrupting flash programming sequences. All programming, debug, and test interfaces are disabled when maximum device security is enabled. IO Subsystem Peripheral Interconnect (MMIO,PPU) PCLK 49x GPIO_STD, 8x GPIO_ENH, 24x GPIO_SMC, 18x HSIO_STD, 43x HSIO_STDLN, 22x HSIO_ENH, 4x HSIO_ENH_DIFF CPU Subsystem System Interconnect (Multi Layer AXI/AHB, IPC, MPU/SMPU) High Speed I/O Matrix, Smart I/O, Boundary Scan CYT4DN MXS40-HT ASIL-B Digital DFT Test Analog DFT System Resources Power Reset Sleep Control PWRSYS-HT REF POR Reset Control TestMode Entry XRES LVD BOD DeepSleep Hibernate Active/Sleep LowePowerActive/Sleep Power Modes OVD Clock Clock Control IMO WDT CSV 8xPLL ECO FLL 1x Smart IO SWJ/ETM/ITM/CTI NVIC, MPU, AXI Cortex M7 320 MHz FPU (SP/DP) D$ 16KB I$ 16KB AHBS AHBP ITCM 64 KB DTCM 64 KB SWJ/ETM/ITM/CTI NVIC, MPU, AXI Cortex M7 320 MHz FPU (SP/DP) D$ 16 KB I$ 16 KB AHBS AHBP ITCM 64 KB DTCM 64 KB eCT FLASH 6336 KB Code-flash + 128 KB Work-flash FLASH Controller 8 KB $ Prog. Analog SAR ADC (12-bit) x1 RTC 2xILO SARMUX 48 ch CRYPTO AES,SHA,CRC, TRNG,RSA,ECC Initiator/MMIO SWJ/MTB/CTI MUL, NVIC, MPU Cortex M0+ 100 MHz SRAM0 256 KB SRAM Controller ROM 64 KB ROM Controller LDO WCO SRAM1 256 KB SRAM Controller GFX Subsystem GFX Interconnect (AXI) VRAM 4096 KB VRAM Controller LPECO SRAM2 128 KB SRAM Controller 3x MCWDT Notes 4. GPIO_STD supporting 2.7 V to 5.5 V VDDIO range. 5. GPIO_ENH supporting 2.7 V to 5.5 V VDDIO range with higher currents at lower voltages. 6. GPIO_SMC supporting 2.7 V to 5.5 V VDDIO range with currents higher than GPIO_ENH. 7. HSIO_STD/HSIO_STDLN supporting 3.0 V to 3.6 V VDDIO range with high-speed signaling and programmable drive strength. 8. HSIO_ENH and HSIO_ENH_PDIFF supporting 1.7 V to 2.0 V VDDIO range. |
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