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CYT4DNJBJS датащи(PDF) 78 Page - Infineon Technologies AG

номер детали CYT4DNJBJS
подробное описание детали  TRAVEO™ T2G 32-bit Automotive MCU Based on Arm® Cortex®-M7 dual
PDF  209 Pages
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производитель  INFINEON [Infineon Technologies AG]
домашняя страница  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

CYT4DNJBJS датащи(HTML) 78 Page - Infineon Technologies AG

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Datasheet
78
002-24601 Rev. *I
2023-02-14
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Peripheral protection unit fixed structure pairs
83
MCWDT0_CONFIG
0x40268000
0x00000080 MCWDT #0 configuration
84
MCWDT1_CONFIG
0x40268100
0x00000080 MCWDT #1 configuration
85
MCWDT2_CONFIG
0x40268200
0x00000080 MCWDT #2 configuration
86
MCWDT0_MAIN
0x40268080
0x00000040 MCWDT #0 main
87
MCWDT1_MAIN
0x40268180
0x00000040 MCWDT #1 main
88
MCWDT2_MAIN
0x40268280
0x00000040 MCWDT #2 main
89
WDT_CONFIG
0x4026C000
0x00000020 System WDT configuration
90
WDT_MAIN
0x4026C040
0x00000020 System WDT main
91
BACKUP_BACKUP
0x40270000
0x00010000 SRSS backup
92
DW0_DW
0x40280000
0x00000100 P-DMA#0 main
93
DW1_DW
0x40290000
0x00000100 P-DMA#1 main
94
DW0_DW_CRC
0x40280100
0x00000080 P-DMA#0 CRC
95
DW1_DW_CRC
0x40290100
0x00000080 P-DMA#1 CRC
96
DW0_CH_STRUCT0_CH
0x40288000
0x00000040 P-DMA#0 Channel #0
97
DW0_CH_STRUCT1_CH
0x40288040
0x00000040 P-DMA#0 Channel #1
98
DW0_CH_STRUCT2_CH
0x40288080
0x00000040 P-DMA#0 Channel #2
99
DW0_CH_STRUCT3_CH
0x402880C0
0x00000040 P-DMA#0 Channel #3
100
DW0_CH_STRUCT4_CH
0x40288100
0x00000040 P-DMA#0 Channel #4
101
DW0_CH_STRUCT5_CH
0x40288140
0x00000040 P-DMA#0 Channel #5
102
DW0_CH_STRUCT6_CH
0x40288180
0x00000040 P-DMA#0 Channel #6
103
DW0_CH_STRUCT7_CH
0x402881C0
0x00000040 P-DMA#0 Channel #7
104
DW0_CH_STRUCT8_CH
0x40288200
0x00000040 P-DMA#0 Channel #8
105
DW0_CH_STRUCT9_CH
0x40288240
0x00000040 P-DMA#0 Channel #9
106
DW0_CH_STRUCT10_CH
0x40288280
0x00000040 P-DMA#0 Channel #10
107
DW0_CH_STRUCT11_CH
0x402882C0
0x00000040 P-DMA#0 Channel #11
108
DW0_CH_STRUCT12_CH
0x40288300
0x00000040 P-DMA#0 Channel #12
109
DW0_CH_STRUCT13_CH
0x40288340
0x00000040 P-DMA#0 Channel #13
110
DW0_CH_STRUCT14_CH
0x40288380
0x00000040 P-DMA#0 Channel #14
111
DW0_CH_STRUCT15_CH
0x402883C0
0x00000040 P-DMA#0 Channel #15
112
DW0_CH_STRUCT16_CH
0x40288400
0x00000040 P-DMA#0 Channel #16
113
DW0_CH_STRUCT17_CH
0x40288440
0x00000040 P-DMA#0 Channel #17
114
DW0_CH_STRUCT18_CH
0x40288480
0x00000040 P-DMA#0 Channel #18
115
DW0_CH_STRUCT19_CH
0x402884C0
0x00000040 P-DMA#0 Channel #19
116
DW0_CH_STRUCT20_CH
0x40288500
0x00000040 P-DMA#0 Channel #20
117
DW0_CH_STRUCT21_CH
0x40288540
0x00000040 P-DMA#0 Channel #21
118
DW0_CH_STRUCT22_CH
0x40288580
0x00000040 P-DMA#0 Channel #22
119
DW0_CH_STRUCT23_CH
0x402885C0
0x00000040 P-DMA#0 Channel #23
120
DW0_CH_STRUCT24_CH
0x40288600
0x00000040 P-DMA#0 Channel #24
121
DW0_CH_STRUCT25_CH
0x40288640
0x00000040 P-DMA#0 Channel #25
122
DW0_CH_STRUCT26_CH
0x40288680
0x00000040 P-DMA#0 Channel #26
123
DW0_CH_STRUCT27_CH
0x402886C0
0x00000040 P-DMA#0 Channel #27
124
DW0_CH_STRUCT28_CH
0x40288700
0x00000040 P-DMA#0 Channel #28
125
DW0_CH_STRUCT29_CH
0x40288740
0x00000040 P-DMA#0 Channel #29
126
DW0_CH_STRUCT30_CH
0x40288780
0x00000040 P-DMA#0 Channel #30
127
DW0_CH_STRUCT31_CH
0x402887C0
0x00000040 P-DMA#0 Channel #31
Table 22-1
PPU fixed structure pairs (continued)
Pair
No.
PPU Fixed Structure Pair
Address
Size
Description



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