CYT4DNJBJS datasheet(12/209 Pages) INFINEON

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Datasheet

002-24601 Rev. *I

2023-02-14

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M7 dual

Functional description

3.2

System resources

3.2.1

Power system

The power system ensures that the supply voltage levels meet the requirements of each power mode, and

provides a full-system reset when these levels are not valid. Internal power-on reset (POR) guarantees full-chip

reset during the initial power ramp.

Three BOD circuits monitor the external supply voltages (VDDD, VDDA_ADC, VCCD). The BOD on VDDD and VCCD is

initially enabled and cannot be disabled. The BOD on VDDA_ADCisinitiallydisabledandcanbeenabledbytheuser.

For the external supplies VDDD and VDDA_ADC, BOD circuits are software-configurable with two settings; a 2.7-V

minimum voltage that is robust for all internal signaling, and a 3.0-V minimum voltage, which is also robust for

all I/O specifications (which are guaranteed at 2.7 V). The BOD on VCCD is provided as a safety measure and is not

a robust detector.

Three over-voltage detection (OVD) circuits are provided for monitoring external supplies (VDDD, VDDA_ADC, VCCD),

and overcurrent detection circuits (OCD) for monitoring internal and external regulators. OVD thresholds on VDDD

and VDDA_ADC are configurable with two settings; a 5.0-V and 5.5-V maximum voltage.

Two voltage detection circuits are provided to monitor the external supply voltage (VDDD) for falling and rising

levels, each configurable for one of the 26 selectable levels.

All BOD, OVD, and OCD circuits on VDDD and VCCD generate a reset, because these protect the CPUs and fault logic.

The BOD and OVD circuits on VDDA_ADC can be configured to generate either a reset, or a fault.

3.2.2

Regulators

CYT4DN contains two regulators that provide power to the low-voltage core transistors: DeepSleep, and core

internal. These regulators accept a 2.7-V to 5.5-V VDDD supply and provide a low-noise 1.1-V supply to various

parts of the device. These regulators are automatically enabled and disabled by hardware and firmware when

switching between power modes. The core internal regulator operates in Active mode, and provide power to the

CPU subsystem and associated peripherals.

3.2.2.1

DeepSleep

The DeepSleep regulator is used to maintain power in a small number of blocks when in DeepSleep mode. These

blocks include the ILO and WDT timers, BOD detector, SCB0, SRAM memories, Smart I/O, and other configuration

memories. The DeepSleep regulator is enabled when in DeepSleep mode, and the core internal regulator is

disabled. It is disabled when XRES_L is asserted (LOW) and when the core internal regulator is disabled.

3.2.2.2

Core internal

The core internal regulator supports load currents up to 300 mA, and is operational during device start-up (boot

process), and in Active/Sleep modes. (Graphics subsystem is not supported)

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