CYT4DNJBJS datasheet(80/209 Pages) INFINEON

80 / 209 page

Datasheet

002-24601 Rev. *I

2023-02-14

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M7 dual

Peripheral protection unit fixed structure pairs

173

DW1_CH_STRUCT1_CH

0x40298040

0x00000040 P-DMA#1 Channel #1

174

DW1_CH_STRUCT2_CH

0x40298080

0x00000040 P-DMA#1 Channel #2

175

DW1_CH_STRUCT3_CH

0x402980C0

0x00000040 P-DMA#1 Channel #3

176

DW1_CH_STRUCT4_CH

0x40298100

0x00000040 P-DMA#1 Channel #4

177

DW1_CH_STRUCT5_CH

0x40298140

0x00000040 P-DMA#1 Channel #5

178

DW1_CH_STRUCT6_CH

0x40298180

0x00000040 P-DMA#1 Channel #6

179

DW1_CH_STRUCT7_CH

0x402981C0

0x00000040 P-DMA#1 Channel #7

180

DW1_CH_STRUCT8_CH

0x40298200

0x00000040 P-DMA#1 Channel #8

181

DW1_CH_STRUCT9_CH

0x40298240

0x00000040 P-DMA#1 Channel #9

182

DW1_CH_STRUCT10_CH

0x40298280

0x00000040 P-DMA#1 Channel #10

183

DW1_CH_STRUCT11_CH

0x402982C0

0x00000040 P-DMA#1 Channel #11

184

DW1_CH_STRUCT12_CH

0x40298300

0x00000040 P-DMA#1 Channel #12

185

DW1_CH_STRUCT13_CH

0x40298340

0x00000040 P-DMA#1 Channel #13

186

DW1_CH_STRUCT14_CH

0x40298380

0x00000040 P-DMA#1 Channel #14

187

DW1_CH_STRUCT15_CH

0x402983C0

0x00000040 P-DMA#1 Channel #15

188

DW1_CH_STRUCT16_CH

0x40298400

0x00000040 P-DMA#1 Channel #16

189

DW1_CH_STRUCT17_CH

0x40298440

0x00000040 P-DMA#1 Channel #17

190

DW1_CH_STRUCT18_CH

0x40298480

0x00000040 P-DMA#1 Channel #18

191

DW1_CH_STRUCT19_CH

0x402984C0

0x00000040 P-DMA#1 Channel #19

192

DW1_CH_STRUCT20_CH

0x40298500

0x00000040 P-DMA#1 Channel #20

193

DW1_CH_STRUCT21_CH

0x40298540

0x00000040 P-DMA#1 Channel #21

194

DW1_CH_STRUCT22_CH

0x40298580

0x00000040 P-DMA#1 Channel #22

195

DW1_CH_STRUCT23_CH

0x402985C0

0x00000040 P-DMA#1 Channel #23

196

DW1_CH_STRUCT24_CH

0x40298600

0x00000040 P-DMA#1 Channel #24

197

DW1_CH_STRUCT25_CH

0x40298640

0x00000040 P-DMA#1 Channel #25

198

DW1_CH_STRUCT26_CH

0x40298680

0x00000040 P-DMA#1 Channel #26

199

DW1_CH_STRUCT27_CH

0x402986C0

0x00000040 P-DMA#1 Channel #27

200

DW1_CH_STRUCT28_CH

0x40298700

0x00000040 P-DMA#1 Channel #28

201

DW1_CH_STRUCT29_CH

0x40298740

0x00000040 P-DMA#1 Channel #29

202

DW1_CH_STRUCT30_CH

0x40298780

0x00000040 P-DMA#1 Channel #30

203

DW1_CH_STRUCT31_CH

0x402987C0

0x00000040 P-DMA#1 Channel #31

204

DW1_CH_STRUCT32_CH

0x40298800

0x00000040 P-DMA#1 Channel #32

205

DW1_CH_STRUCT33_CH

0x40298840

0x00000040 P-DMA#1 Channel #33

206

DW1_CH_STRUCT34_CH

0x40298880

0x00000040 P-DMA#1 Channel #34

207

DW1_CH_STRUCT35_CH

0x402988C0

0x00000040 P-DMA#1 Channel #35

208

DW1_CH_STRUCT36_CH

0x40298900

0x00000040 P-DMA#1 Channel #36

209

DW1_CH_STRUCT37_CH

0x40298940

0x00000040 P-DMA#1 Channel #37

210

DW1_CH_STRUCT38_CH

0x40298980

0x00000040 P-DMA#1 Channel #38

211

DW1_CH_STRUCT39_CH

0x402989C0

0x00000040 P-DMA#1 Channel #39

212

DW1_CH_STRUCT40_CH

0x40298A00

0x00000040 P-DMA#1 Channel #40

213

DW1_CH_STRUCT41_CH

0x40298A40

0x00000040 P-DMA#1 Channel #41

214

DW1_CH_STRUCT42_CH

0x40298A80

0x00000040 P-DMA#1 Channel #42

215

DW1_CH_STRUCT43_CH

0x40298AC0

0x00000040 P-DMA#1 Channel #43

216

DW1_CH_STRUCT44_CH

0x40298B00

0x00000040 P-DMA#1 Channel #44

217

DW1_CH_STRUCT45_CH

0x40298B40

0x00000040 P-DMA#1 Channel #45

Table 22-1

PPU fixed structure pairs (continued)

Pair

No.

PPU Fixed Structure Pair

Address

Size

Description

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