CYT4DNJBJS datasheet(18/209 Pages) INFINEON

18 / 209 page

Datasheet

002-24601 Rev. *I

2023-02-14

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M7 dual

Functional description

3.3.5.3

SPI interface

The SPI configuration supports full Motorola SPI, TI Synchronous Serial Protocol (SSP, essentially adds a start

pulse that is used to synchronize SPI-based Codecs), and National Microwire (a half-duplex form of SPI). The SPI

interface can use the FIFO. The SPI interface operates with up to a 12.5-MHz SPI Clock. SCB also supports EZSPI[14]

mode.

SCB0 supports the following additional features:

• Operable as a slave in DeepSleep mode

•I2C slave EZ (EZI2C[14]) mode with up to 256-B data buffer for multi-byte communication without CPU

intervention

•I2C slave externally-clocked operations

• Command/response mode with a 512-B data buffer for multi-byte communication without CPU intervention

3.3.6

Controller area network flexible data-rate (CAN FD)

CYT4DN supports two CAN FD controller blocks, each supporting two CAN FD channel. All CAN FD controllers are

compliant with the ISO 11898-1:2015 standard; an ISO 16845:2015 certificate is available. It also implements the

time-triggered CAN (TTCAN) protocol specified in ISO 11898-4 (TTCAN protocol levels 1 and 2) completely in

hardware. All functions concerning the handling of messages are implemented by the Rx and Tx handlers. The Rx

handler manages message acceptance filtering, transfer of received messages from the CAN core to a message

RAM, and provides receive-message status. The Tx handler is responsible for the transfer of transmit messages

from the message RAM to the CAN core, and provides transmit-message status.

3.3.7

Local interconnect network (LIN)

CYT4DN contains up to two LIN channels. Each channel supports transmission/reception of data following the

LIN protocol according to ISO standard 17987. Each LIN channel connects to an external transceiver through a

3-pin interface (including an enable function) and supports master and slave functionality. Each block also

supports classic and enhanced checksum, along with break detection during message reception and wake-up

signaling. Break detection, sync field, checksum calculations, and error interrupts are handled in hardware.

3.3.8

Clock extension peripheral interface (CXPI)

CYT4DN contains up to four CXPI channels compliant with JASO D015 and ISO standard 20794 including the

controller specification.

Each channel supports:

• Master and slave functionality

• Polling and event trigger method for both normal and long frames

• Non-return to zero (NRZ) and PWM signaling modes

• Collision resolution and carries sense multiple access

• Wakeup pulse generation and detection

• CRC8 and CRC16 for both normal and long frames

•Error detection

• Dedicated FIFO (16 B) for transmit and receive

3.3.9

Ethernet MAC

CYT4DN supports one Ethernet channel with transfer rates of 10, 100, or 1000 (RGMII) Mbps. The input/output

frames and flow control are compliant with the Ethernet/IEEE 802.3az standard and also IEEE-1588

precision-time protocol (PTP). CYT4DN supports half/full-duplex data transport using external PHY devices. The

MAC supports glue-free connection to PHYs through IEEE standard MII, RMII, and RGMII interfaces. The device also

Note

14.The Easy SPI (EZSPI) protocol is based on the Motorola SPI protocol operating in any mode (0, 1, 2, or 3). It allows communication

between master and slave while reducing the need for CPU intervention.

15.The Easy I2C (EZI2C) protocol is a unique communication scheme built on top of the I2C protocol by Infineon. It uses a meta protocol

around the standard I2C protocol to communicate to an I2C slave using indexed memory transfers. This reduces the need for CPU

intervention.

CYT4DNJBJS датащи(PDF) 18 Page - Infineon Technologies AG

CYT4DNJBJS датащи(HTML) 18 Page - Infineon Technologies AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL