CYT4DNJBJS datasheet(13/209 Pages) INFINEON

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Datasheet

002-24601 Rev. *I

2023-02-14

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M7 dual

Functional description

3.2.3

PMIC control module[9]

An internal PMIC module is available to control an external PMIC. The PMIC control module manages the handoff

between the internal active regulator, used only for boot, and the external PMIC.

Both the core internal and external PMIC require an external bulk storage capacitor connected to the VCCD pin.

This capacitor provides charge under the dynamic loads of the low-voltage core transistors.

Figure 3-1

Sample PMIC control interface

3.2.4

Clock system

The CYT4DN clock system provides clocks to all subsystems that require them, and glitch-free switching between

different clock sources. In addition, the clock system ensures that no metastable conditions occur.

The clock system for CYT4DN consists of the 8-MHz IMO, two ILOs, four watchdog timers, eight PLLs, an FLL, five

clock supervisors (CSV), a 7.2- to 33.34-MHz ECO, a 3.99- to 8.01-MHz LPECO, and a 32.768-kHz WCO.

The clock system supports three main clock domains: CLK_HF, CLK_SLOW, and CLK_LF.

• CLK_HFx are the Active mode clocks. Each can use any of the high frequency clock sources including IMO,

EXT_CLK, ECO, LPECO, FLL, or PLL

• CLK_SLOW provides a reference clock for the Cortex®-CM0+ CPU, Crypto, P-/M-DMA, and other slow infra-

structure blocks of CPU subsystem

• CLK_LF is a DeepSleep domain clock and provides a reference clock for the MCWDT or RTC modules. The

reference clock for the CLK_LF domain is either disabled or selectable from ILO0, ILO1, or WCO.

Table 3-1

CLK_HF destinations

Name

Description

CLK_HF0

CPUSS (Memories, CLK_SLOW, Peripherals)

CLK_HF1

CPUSS (Cortex®-M7 CPU 0, 1)

CLK_HF2

CAN FD, CXPI, LIN, SCB, SAR

CLK_HF3

Event Generator, Clock output (CLK_EXT)

VCCD

PMIC_EN

PMIC_STATUS

Switching node

VDDD

Power Good

(PG)

Enable

(EN)

2.7V – 5.5V Power rail

Vin

External

PMIC

Power Good

TRAVEOTM T2G

Core supply rail

VDDD or PMIC_EN

- PMIC EN pin polarity is HIGH for enable. PMIC PG pin polarity is HIGH for power good.

- If EN pin of PMIC does not have the internal pull-down resistor, an external pull-down resistor must be placed to keep the PMIC disabled during power-on reset.

- See the Electrical Specifications section for more details on CS1.

CS1

Note

9. While CYT4DN can control various external PMICs, it is verified to work with both the Cypress S6BP501A and Infineon TLS208D1.

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