CYT4DNJBJS datasheet(21/209 Pages) INFINEON

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Datasheet

002-24601 Rev. *I

2023-02-14

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M7 dual

Functional description

3.5.1

GPIOs

Three types of GPIOs are supported:

• GPIO_STD, GPIO_ENH, and GPIO_SMC

These implement the following:

• Configurable input threshold (CMOS, TTL, or Automotive)

• Hold mode for latching previous state (used for retaining the I/O state in DeepSleep mode)

• Analog input mode (input and output buffers disabled)

• Edge-triggered interrupts on rising edge, falling edge, or on both the edges, on pin basis

3.5.1.1

GPIO Standard (GPIO_STD)

Supports standard automotive signaling across the 2.7-V to 5.5-V VDDIO range. GPIO Standard I/Os have multiple

configurable drive levels, drive modes, and selectable input levels.

3.5.1.2

GPIO Enhanced (GPIO_ENH)

Supports extended functionality automotive signaling across the 2.7-V to 5.5-V VDDIO range with higher currents

at lower voltages (full I2C timing support, slew-rate control).

3.5.1.3

GPIO SMC (GPIO_SMC)

Provides significant drive strength compared to GPIO_STD and GPIO_ENH (supports 30-mA drive).

3.5.2

HSIO

These I/Os are optimized exclusively for high-speed signaling and do not support slew-rate control, DeepSleep

operation, POR mode control, analog connections, or non-CMOS signaling levels. HSIO support programmable

drive strength. They are available only in Active mode.

3.5.2.1

HSIO Standard (HSIO_STD)

Supports clocking and signaling up to 125 MHz. Supports high-speed peripherals such as Graphics input/output.

Also supports holding state during DeepSleep mode.

3.5.2.2

HSIO Standard Low Noise (HSIO_STDLN)

This I/O supports clocking and signaling up to 133 MHz. Supports high-speed peripherals such as Graphics

input/output, and Ethernet. Also supports holding state during DeepSleep mode. Low noise version optimizes

the noise generated by having specific modes for each interface support.

3.5.2.3

HSIO Enhanced (HSIO_ENH)[18]

Supports clocking and signaling up to 166 MHz. Supports high-speed peripherals such as QSPI and xSPI.

3.5.2.4

HSIO Enhanced Differential (HSIO_ENH_PDIFF)[18]

Supports clocking and signaling up to 200 MHz, to output SMIF clocks (normal and inverted).

3.5.3

Port nomenclature

Px.y describes a particular bit “y” available within an I/O port “x.”

For example, P4.2 reads “port 4, bit 2”.

3.5.4

Smart I/O

Smart I/O allows Boolean operations on signals going to the I/O from the subsystems of the chip or on signals

coming into the chip. CYT4DN has one Smart I/O block. Operation can be synchronous or asynchronous and the

blocks operate in all device power modes except for the Hibernate mode.

Note

18.VDDIO_SMIF_HV provides the supply for the HSIO_ENH and HSIO_ENH_PDIFF pre-drivers.

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