CYT4DNJBJS datasheet(101/209 Pages) INFINEON

101 / 209 page

Datasheet

101

002-24601 Rev. *I

2023-02-14

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M7 dual

Electrical specifications

26.2

Device-level specifications

Table 26-2

Recommended operating conditions

Spec ID

Parameter

Description

Min

Typ

Max

Units

Details/conditions

Recommended operating conditions

SID40

VDDD, VDDA_ADC,

VDDIO_GPIO,

VDDIO_SMC,

Power supply voltage[62]

2.7[63]

–5.5[64]

VDDIO_GPIO

(VDDIO_GPIO_0/1/2)

SID40A

VDDIO_EFP

Power supply voltage for eFuse

programming[65]

3.0

–

5.5

VDDIO_GPIO_0 for this

product, when

programming eFuses

SID40B

VDDIO_HSIO

Power supply voltage

3.0

3.3

3.6

SID40D

VDDIO_SMIF

Power supply voltage (VDDIO_SMIF).

Supply for 1.8 V I/Os.

1.7

1.8

1.95

Disable the IO cell input

buffer before shutting off

any of the IO supply

voltages (VDDIO_SMIF or

VDDIO_SMIF_HV).

SID40DA

VDDIO_SMIF_HV

Power supply voltage (VDDIO_SMIF_HV).HV

supply for pre-drivers of HSIO_ENH I/Os.

3.0

3.3

3.6

SID40E

VDDPLL_FPD0[68, 69]

Power supply voltage (VDDPLL_FPD0).

Supply for FPD-link PLLs.

1.09

1.15

1.21

SID40F

VDDHA_FPD0

Power supply voltage (VDDHA_FPD0).

Supply for FPD-link line drivers.

3.0

3.3

3.6

SID40G

VDDA_FPD0[68, 69]

Power supply voltage (VDDA_FPD0).

Core-supply for FPD-link.

1.09

1.15

1.21

SID40E_1

VDDPLL_FPD1[68, 69]

Power supply voltage (VDDPLL_FPD1).

Supply for FPD-link PLLs.

1.09

1.15

1.21

SID40F_1

VDDHA_FPD1

Power supply voltage (VDDHA_FPD1).

Supply for FPD-link line drivers.

3.0

3.3

3.6

SID40G_1

VDDA_FPD1[68, 69]

Power supply voltage (VDDA_FPD1).

Core-supply for FPD-link.

1.09

1.15

1.21

SID40H

VDDA_MIPI[68]

Power supply voltage (VDDA_MIPI). Supply

for MIPI D-PHY.

1.09

1.15

1.21

SID40J

VCCD[68]

External VCCD power supply

1.09

1.15

1.21

External VCCD power supply

range when externally

supplied at VCCD. VCCDmust

not be driven by an external

supply at startup. See

related application note for

correct startup sequence.

SID41

CS1

Smoothing capacitor[66, 67]

30.8

103.4

µF

SID43

VDDA_DAC

High voltage supply

3.0

3.3

3.6

Notes

62.Ensure VDDIO_GPIO_2 ≥ 0.8 × VDDA_ADC when SARMUX0 is enabled.

63.3.0 V ±10% is supported with a lower BOD setting option. This setting provides robust protection for internal timing but BOD reset occurs at

a voltage below the specified operating conditions. A higher BOD setting option is available (consistent with down to 3.0 V) and guarantees

that all operating conditions are met.

64.5.0 V ±10% is supported with a higher OVD setting option. This setting provides robust protection for internal and interface timing, but OVD

reset occurs at a voltage above the specified operating conditions. A lower OVD setting option is available (consistent with up to 5.0 V) and

guarantees that all operating conditions are met. Voltage overshoot to a higher OVD setting range for VDDD and VDDA_ADC is permissible,

provided the duration is less than 2 hours cumulated. Note that during overshoot voltage condition electrical parameters are not guaranteed.

65.eFuse programming must be executed with the part in a “quiet” state, with minimal activity (preferably only JTAG or a single LIN/CAN channel

on VDDIO_GPIO domain).

66.Only one smoothing capacitor, CS1 is required per chip (not per VCCD pin). The VCCD pins should be connected together to ensure a

low-impedance connection (see the recommendation in Figure 26-2).

67.Capacitors used for power supply decoupling or filtering are operated under a continuous DC-bias. Many capacitors used with DC power

across them provide less than their target capacitance, and their capacitance is not constant across their working voltage range. When

selecting capacitors for use with this device, ensure that the selected components provide the required capacitance under the specific

operating conditions of temperature and voltage used in your design. While the temperature coefficient is normally found within a parts

catalog (such as, X7R, C0G, Y5V), the matching voltage coefficient may only be available on the component datasheet or direct from the

manufacturer. Use of components that do not provide the required capacitance under the actual operating conditions may cause the device

to operate to less than datasheet specifications.

68.Analog and digital supply rails to be shorted on the PCB (VDDPLL_FPD0 = VDDPLL_FPD1 = VDDA_FPD0 = VDDA_FPD1 = VDDA_MIPI = VCCD). These supply

rails must be connected to the same power supply of VCCD. This supply voltage needs to be filtered in order to eliminate any PLL jitters. It is

recommended to use a noise filter to reduce the noise ripple for the FPD-LINK and MIPI-PHY supply.

69.After XRES_L release, internal LDO will be ON, and VCCD = VDDPLL_FPD = VDDA_FPD = 1.15 V, only then hand over to external PMIC is allowed.

CYT4DNJBJS датащи(PDF) 101 Page - Infineon Technologies AG

CYT4DNJBJS датащи(HTML) 101 Page - Infineon Technologies AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL