CYT4DNJBJS datasheet(2/209 Pages) INFINEON

2 / 209 page

Datasheet

002-24601 Rev. *I

2023-02-14

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M7 dual

Features

• CPU subsystem

- Two 320-MHz 32-bit Arm® Cortex®-M7 CPUs, each with

• Single-cycle multiply

•Single/double-precision floating point unit (FPU)

• 16-KB data cache, 16-KB instruction cache

• Memory protection unit (MPU)

• 64-KB instruction and 64-KB data Tightly-Coupled Memories (TCM)

- One 100-MHz 32-bit Arm® Cortex®-M0+ CPU with

• Single-cycle multiply

• Memory protection unit

- Inter-processor communication in hardware

- Three DMA controllers

• Peripheral DMA controller #0 (P-DMA0) with 76 channels

• Peripheral DMA controller #1 (P-DMA1) with 84 channels

• Memory DMA (AHB) controller (M-DMA0) with 8 channels

• Memory DMA (AXI) controller (M-DMA1) with 4 channels

• Integrated memories

- 6336-KB code-flash with an additional 128-KB of work-flash

• Read-While-Write (RWW) allows updating the code-flash/work-flash while executing from it

• Single- and dual-bank modes (specifically for Firmware update Over The Air [FOTA])

• Flash programming through SWD/JTAG interface

- 640-KB of SRAM with selectable retention granularity

• Crypto engine[1]

- Supports Enhanced Secure Hardware Extension (eSHE) and Hardware Security Module (HSM)

- Secure boot and authentication

• Using digital signature verification[1]

•Using fast secure boot

- AES: 128-bit blocks, 128-/192-/256-bit keys

-3DES[1]: 64-bit blocks, 64-bit key

-Vector unit[1] supporting asymmetric key cryptography such as Rivest-Shamir-Adleman (RSA) and Elliptic

Curve (ECC)

- SHA-1/2/3[1]: SHA-512, SHA-256, SHA-160 with variable length input data

-CRC[1]: supports CCITT CRC16 and IEEE-802.3 CRC32

- True random number generator (TRNG) and pseudo random number generator (PRNG)

- Galois/Counter Mode (GCM)

• Functional safety for ASIL-B

- Memory protection unit (MPU)

- Shared memory protection unit (SMPU)

- Peripheral protection unit (PPU)

-Watchdog timer (WDT)

- Multi-counter watchdog timer (MCWDT)

-Low-voltage detector (LVD)

-Brown-out detection (BOD)

- Over-voltage detection (OVD)

-Overcurrent detection (OCD)

-Clock supervisor (CSV)

• Supported in all power modes

- Hardware error correction (SECDED ECC) on all safety-critical memories (SRAM, flash, TCM)

Note

1. The Crypto engine features are available on select MPNs.

CYT4DNJBJS датащи(PDF) 2 Page - Infineon Technologies AG

CYT4DNJBJS датащи(HTML) 2 Page - Infineon Technologies AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL