CYT4DNJBJS datasheet(72/209 Pages) INFINEON

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Datasheet

002-24601 Rev. *I

2023-02-14

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M7 dual

Faults

Table 21-1

Fault assignments

Fault

Source

Description

CPUSS_MPU_VIO_0

CM0+ SMPU violation

DATA0[31:0]: Violating address.

DATA1[0]: User read.

DATA1[1]: User write.

DATA1[2]: User execute.

DATA1[3]: Privileged read.

DATA1[4]: Privileged write.

DATA1[5]: Privileged execute.

DATA1[6]: Non-secure.

DATA1[11:8]: Master identifier.

DATA1[15:12]: Protection context identifier.

DATA1[31]: '0' MPU violation; '1': SMPU violation.

CPUSS_MPU_VIO_1

Crypto SMPU violation. See CPUSS_MPU_VIO_0 description.

CPUSS_MPU_VIO_2

P-DMA0 MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.

CPUSS_MPU_VIO_3

P-DMA1 MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.

CPUSS_MPU_VIO_4

M-DMA0 MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.

CPUSS_MPU_VIO_9

ETH0 MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.

CPUSS_MPU_VIO_11

AXI M-DMA1 MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.

CPUSS_MPU_VIO_12

VIDEOSS0 MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.

CPUSS_MPU_VIO_13

CM7_1 MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.

CPUSS_MPU_VIO_14

CM7_0 MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.

CPUSS_MPU_VIO_15

Test Controller MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.

CPUSS_CM7_0_CACHE_C_ECC

Correctable ECC error in CM7_0 Cache memories

DATA0[16:2]: location information: Tag/Data SRAM, Way, Index and line Offset, see CM7 UGRM

IEBR0/DEBR0 description for details.

DATA0[31]: 0=Instruction cache, 1= Data cache

CPUSS_CM7_0_CACHE_NC_ECC

Non Correctable ECC error in CM7_0 Cache memories. See CPUSS_CM7_0_CACHE_C_ECC

description

CPUSS_CM7_0_TCM_C_ECC

Correctable ECC error in CM7_0 TCM memory

DATA0[23:2]: Violating address.

DATA1[7:0]: Syndrome of code word (at address offset 0x0).

DATA1[31:30]: 0= ITCM, 2=D0TCM, 3=D1TCM

CPUSS_CM7_0_TCM_NC_ECC

Non Correctable ECC error in CM7_0 TCM memory.

See CPUSS_CM7_0_TCM_C_ECC description.

CPUSS_CM7_1_CACHE_C_ECC

Correctable ECC error in CM7_1 Cache memories.

See CPUSS_CM7_0_CACHE_C_ECC description

CPUSS_CM7_1_CACHE_NC_ECC

Non Correctable ECC error in CM7_1 Cache memories. See CPUSS_CM7_0_CACHE_C_ECC

description

CPUSS_CM7_1_TCM_C_ECC

CPU CM7_1 TCM memory correctable ECC violation.

See CPUSS_CM7_0_TCM_C_ECC description.

CPUSS_CM7_1_TCM_NC_ECC

CPU CM7_1 TCM memory non-correctable ECC violation.

See CPUSS_CM7_0_TCM_C_ECC description.

PERI_PERI_C_ECC

Peripheral protection SRAM correctable ECC violation

DATA0[10:0]: Violating address.

DATA1[7:0]: Syndrome of SRAM word.

PERI_PERI_NC_ECC

Peripheral protection SRAM non-correctable ECC violation

PERI_MS_VIO_0

CM0+ Peripheral Master Interface PPU violation

DATA0[31:0]: Violating address.

DATA1[0]: User read.

DATA1[1]: User write.

DATA1[2]: User execute.

DATA1[3]: Privileged read.

DATA1[4]: Privileged write.

DATA1[5]: Privileged execute.

DATA1[6]: Non-secure.

DATA1[11:8]: Master identifier.

DATA1[15:12]: Protection context identifier.

DATA1[31:28]: “0”: master interface, PPU violation, “1': timeout detected, “2”: bus error, other:

undefined.

PERI_MS_VIO_1

CM7_0 Peripheral Master Interface PPU violation.

See PERI_MS_VIO_0 description.

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