CYT4DNJBJS datasheet(96/209 Pages) INFINEON

96 / 209 page

Datasheet

002-24601 Rev. *I

2023-02-14

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M7 dual

Electrical specifications

Table 26-1

Absolute maximum ratings

Spec ID

Parameter

Description

Min

Typ

Max

Units

Details/

conditions

SID10

VDDD_ABS

Power supply voltage (VDDD)[45, 46]

VSS – 0.3

–

VSS + 6.0

See Table 3-4 for

assignment of ports to

supply domains

SID10A

VDDIO_GPIO_ABS

Power supply voltage (VDDIO_GPIO)[46]

VSS – 0.3

–

VSS + 6.0

Applies to all VDDIO_GPIO

sources (VDDIO_GPIO_1/2/3)

See Table 3-4 for

assignment of ports to

supply domains

SID10B

VDDIO_SMC_ABS

Power supply voltage (VDDIO_SMC)[46]

VSS – 0.3

–

VSS + 6.0

See Table 3-4 for

assignment of ports to

supply domains

SID10C

VDDIO_HSIO_ABS

Power supply voltage (VDDIO_HSIO)[46]

VSS – 0.3

–

VSS + 6.0

See Table 3-4 for

assignment of ports to

supply domains

SID10D

VDDIO_SMIF_ABS

Power supply voltage (VDDIO_SMIF)[46]

VSS – 0.3

–

VSS + 2.2

See Table 3-4 for

assignment of ports to

supply domains

SID10E

VDDIO_SMIF_HV_ABS

Power supply voltage (VDDIO_SMIF_HV)[46]

Supply for 1.8 V I/Os

VSS – 0.3

–

VSS + 4.0

See Table 3-4 for

assignment of ports to

supply domains

SID10F

VDDPLL_FPD0_ABS

Power supply voltage (VDDPLL_FPD0)[46]

Supply for FPD-Link PLLs

VSSA_FPD0–

0.3

–

VSSA_FPD0 +

1.21

SID10G

VDDHA_FPD0_ABS

Power supply voltage (VDDHA_FPD0)[46]

Supply for FPD-Link Drivers

VSSA_FPD0–

0.3

–

VSSA_FPD0 +

4.0

SID10H

VDDA_FPD0_ABS

Power supply voltage (VDDA_FPD0)[46]

Core-supply for FPD-Link

VSSA_FPD0–

0.3

–

VSSA_FPD0 +

1.21

SID10F_1

VDDPLL_FPD1_ABS

Power supply voltage (VDDPLL_FPD1)[46]

Supply for FPD-Link PLLs

VSSA_FPD1–

0.3

–

VSSA_FPD1 +

1.21

SID10G_1

VDDHA_FPD1_ABS

Power supply voltage (VDDHA_FPD1)[46]

Supply for FPD-Link Drivers

VSSA_FPD1–

0.3

–

VSSA_FPD1 +

4.0

SID10H_1

VDDA_FPD1_ABS

Power supply voltage (VDDA_FPD1)[46]

Core-supply for FPD-Link

VSSA_FPD1–

0.3

–

VSSA_FPD1 +

1.21

SID10J

VDDA_MIPI_ABS

Power supply voltage (VDDA_MIPI)[46]

Supply for MIPI D-PHY

VSSA_MIPI–

0.3

–

VSSA_MIPI +

1.21

SID45

VDDA_DAC_ABS

Power supply voltage (VDDA_DAC)[46]

Supply for Audio DAC

VSSA_DAC –

0.3

–VSSA_DAC + 4.0

SID11

VDDA_ADC_ABS

Analog power supply voltage

(VDDA_ADC)[46]

Supply for SAR ADC

VSSA_ADC –

0.3

–VSSA_ADC + 6.0

SID12

VREFH_ABS

SAR Analog reference voltage, HIGH[46]

VSSA_ADC –

0.3

–VSSA_ADC + 6.0

VREFH  VDDA_ADC + 0.3 V

SID12A

VREFL_ABS

SAR Analog reference voltage, LOW[46]

VSSA_ADC –

0.3

–VSSA_ADC + 0.3

SID13

VCCD_ABS

Power supply voltage (VCCD)VSS – 0.3

–

VSS + 1.21

SID15A

VI_GPIO_ABS

Input voltage[46]

VSS – 0.5

–

VDDIO_GPIO +

0.5

See Table 3-4 for

assignment of ports to

supply domains

SID15B

VI_SMC_ABS

Input voltage[46]

VSS – 0.5

–

VDDIO_SMC +

0.5

See Table 3-4 for

assignment of ports to

supply domains

SID15C

VI_HSIO_ABS

Input voltage[46]

VSS – 0.5

–

VDDIO_HSIO +

0.5

See Table 3-4 for

assignment of ports to

supply domains

SID15E

VI_SMIF_ABS

Input voltage[46]

VSS – 0.5

–

VDDIO_SMIF +

0.5

See Table 3-4 for

assignment of ports to

supply domains

Notes

45.Ensure that VDDD ≥VDDIO_GPIO_2 ≥VDDIO_GPIO_1.EnsurethatVDDDis turned onbeforeVDDIO_GPIO_1, and VDDIO_GPIO_1 isturned on before

VDDIO_GPIO_2, or all at the same time. Also ensure VDDIO_GPIO_2 ≥ VDDA_ADC and VDDIO_SMC ≥ VDDA_ADC to avoid increased leakage.

Operating the mentioned supplies within the same voltage range (i.e. within 2.7V-3.6 V, respectively within 4.5 V-5.5 V) fulfills being

“equal”.

46..These parameters are based on the condition that VSS = VSSA_ADC = VSSA_DAC = VSSA_MIPI = VSSA_FPD = 0.0 V.

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