CYT4DNJBJS datasheet(73/209 Pages) INFINEON

73 / 209 page

Datasheet

002-24601 Rev. *I

2023-02-14

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M7 dual

Faults

PERI_MS_VIO_2

CM7_1 Peripheral Master Interface PPU violation.

See PERI_MS_VIO_0 description.

PERI_MS_VIO_3

P-DMA0 Peripheral Master Interface PPU violation.

See PERI_MS_VIO_0 description.

PERI_MS_VIO_4

P-DMA1 Peripheral Master Interface PPU violation.

See PERI_MS_VIO_0 description.

PERI_GROUP_VIO_0

Peripheral Group #0 violation.

DATA0[31:0]: Violating address.

DATA1[0]: User read.

DATA1[1]: User write.

DATA1[2]: User execute.

DATA1[3]: Privileged read.

DATA1[4]: Privileged write.

DATA1[5]: Privileged execute.

DATA1[6]: Non-secure.

DATA1[11:8]: Master identifier.

DATA1[15:12]: Protection context identifier.

DATA1[31:28]: “0”: decoder or peripheral bus error, other: undefined.

PERI_GROUP_VIO_1

Peripheral Group #1 violation. See PERI_GROUP_VIO_0 description.

PERI_GROUP_VIO_2

Peripheral Group #2 violation. See PERI_GROUP_VIO_0 description.

PERI_GROUP_VIO_3

Peripheral Group #3 violation. See PERI_GROUP_VIO_0 description.

PERI_GROUP_VIO_4

Peripheral Group #4 violation. See PERI_GROUP_VIO_0 description.

PERI_GROUP_VIO_5

Peripheral Group #5 violation. See PERI_GROUP_VIO_0 description.

PERI_GROUP_VIO_6

Peripheral Group #6 violation. See PERI_GROUP_VIO_0 description.

PERI_GROUP_VIO_8

Peripheral Group #8 violation. See PERI_GROUP_VIO_0 description.

PERI_GROUP_VIO_9

Peripheral Group #9 violation. See PERI_GROUP_VIO_0 description.

PERI_GROUP_VIO_10

Peripheral Group #10 violation. See PERI_GROUP_VIO_0 description.

CPUSS_FLASHC_MAIN_BUS_ERR

Flash controller main flash bus error

FAULT_DATA0[26:0]: Violating address. Append 5'b00010 as most significant bits to derive

32-bit system address.

FAULT_DATA1[11:8]: Master identifier.

CPUSS_FLASHC_MAIN_C_ECC

Flash controller main flash correctable ECC violation

DATA[26:0]: Violating address. Append 5'b00010 as most significant bits to derive 32-bit system

address.

DATA1[7:0]: Syndrome of 64-bit word (at address offset 0x00).

DATA1[15:8]: Syndrome of 64-bit word (at address offset 0x08).

DATA1[23:16]: Syndrome of 64-bit word (at address offset 0x10).

DATA1[31:24]: Syndrome of 64-bit word (at address offset 0x18).

CPUSS_FLASHC_MAIN_NC_ECC

Flash controller main flash non-correctable ECC violation.

See CPUSS_FLASHC_MAIN_C_ECC description.

CPUSS_FLASHC_WORK_BUS_ERR

Flash controller work-flash bus error.

See CPUSS_FLASHC_MAIN_BUS_ERR description.

CPUSS_FLASHC_WORK_C_ECC

Flash controller work flash correctable ECC violation.

DATA0[26:0]: Violating address. Append 5'b00010 as most significant bits to derive 32-bit system

address.

DATA1[6:0]: Syndrome of 32-bit word.

CPUSS_FLASHC_WORK_NC_ECC

Flash controller work-flash non-correctable ECC violation.

See CPUSS_FLASHC_WORK_C_ECC description.

CPUSS_FLASHC_CM0_CA_C_ECC

Flash controller CM0+ cache correctable ECC violation.

DATA0[26:0]: Violating address.

DATA1[6:0]: Syndrome of 32-bit SRAM word (at address offset 0x0).

DATA1[14:8]: Syndrome of 32-bit SRAM word (at address offset 0x4).

DATA1[22:16]: Syndrome of 32-bit SRAM word (at address offset 0x8).

DATA1[30:24]: Syndrome of 32-bit SRAM word (at address offset 0xc).

CPUSS_FLASHC_CM0_CA_NC_ECC

Flash controller CM0+ cache non-correctable ECC violation.

See CPUSS_FLASHC_CM0_CA_C_ECC description.

CPUSS_FM_SRAMC_C_ECC

Flash code storage SRAM memory correctable ECC violation:

DATA0[15:0]: Address location in the eCT Flash SRAM.

DATA1[6:0]: Syndrome of 32-bit SRAM word.

CPUSS_FM_SRAMC_NC_ECC

Flash code storage SRAM memory non-correctable ECC violation:

See CPUSS_FM_SRAMC_C_ECC description.

CPUSS_RAMC0_C_ECC

System memory controller 0 correctable ECC violation:

DATA0[31:0]: Violating address.

DATA1[6:0]: Syndrome of 32-bit SRAM code word.

Table 21-1

Fault assignments (continued)

Fault

Source

Description

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