CYT4DNJBJS datasheet(81/209 Pages) INFINEON

81 / 209 page

Datasheet

002-24601 Rev. *I

2023-02-14

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M7 dual

Peripheral protection unit fixed structure pairs

218

DW1_CH_STRUCT46_CH

0x40298B80

0x00000040 P-DMA#1 Channel #46

219

DW1_CH_STRUCT47_CH

0x40298BC0

0x00000040 P-DMA#1 Channel #47

220

DW1_CH_STRUCT48_CH

0x40298C00

0x00000040 P-DMA#1 Channel #48

221

DW1_CH_STRUCT49_CH

0x40298C40

0x00000040 P-DMA#1 Channel #49

222

DW1_CH_STRUCT50_CH

0x40298C80

0x00000040 P-DMA#1 Channel #50

223

DW1_CH_STRUCT51_CH

0x40298CC0

0x00000040 P-DMA#1 Channel #51

224

DW1_CH_STRUCT52_CH

0x40298D00

0x00000040 P-DMA#1 Channel #52

225

DW1_CH_STRUCT53_CH

0x40298D40

0x00000040 P-DMA#1 Channel #53

226

DW1_CH_STRUCT54_CH

0x40298D80

0x00000040 P-DMA#1 Channel #54

227

DW1_CH_STRUCT55_CH

0x40298DC0

0x00000040 P-DMA#1 Channel #55

228

DW1_CH_STRUCT56_CH

0x40298E00

0x00000040 P-DMA#1 Channel #56

229

DW1_CH_STRUCT57_CH

0x40298E40

0x00000040 P-DMA#1 Channel #57

230

DW1_CH_STRUCT58_CH

0x40298E80

0x00000040 P-DMA#1 Channel #58

231

DW1_CH_STRUCT59_CH

0x40298EC0

0x00000040 P-DMA#1 Channel #59

232

DW1_CH_STRUCT60_CH

0x40298F00

0x00000040 P-DMA#1 Channel #60

233

DW1_CH_STRUCT61_CH

0x40298F40

0x00000040 P-DMA#1 Channel #61

234

DW1_CH_STRUCT62_CH

0x40298F80

0x00000040 P-DMA#1 Channel #62

235

DW1_CH_STRUCT63_CH

0x40298FC0

0x00000040 P-DMA#1 Channel #63

236

DW1_CH_STRUCT64_CH

0x40299000

0x00000040 P-DMA#1 Channel #64

237

DW1_CH_STRUCT65_CH

0x40299040

0x00000040 P-DMA#1 Channel #65

238

DW1_CH_STRUCT66_CH

0x40299080

0x00000040 P-DMA#1 Channel #66

239

DW1_CH_STRUCT67_CH

0x402990C0

0x00000040 P-DMA#1 Channel #67

240

DW1_CH_STRUCT68_CH

0x40299100

0x00000040 P-DMA#1 Channel #68

241

DW1_CH_STRUCT69_CH

0x40299140

0x00000040 P-DMA#1 Channel #69

242

DW1_CH_STRUCT70_CH

0x40299180

0x00000040 P-DMA#1 Channel #70

243

DW1_CH_STRUCT71_CH

0x402991C0

0x00000040 P-DMA#1 Channel #71

244

DW1_CH_STRUCT72_CH

0x40299200

0x00000040 P-DMA#1 Channel #72

245

DW1_CH_STRUCT73_CH

0x40299240

0x00000040 P-DMA#1 Channel #73

246

DW1_CH_STRUCT74_CH

0x40299280

0x00000040 P-DMA#1 Channel #74

247

DW1_CH_STRUCT75_CH

0x402992C0

0x00000040 P-DMA#1 Channel #75

248

DW1_CH_STRUCT76_CH

0x40299300

0x00000040 P-DMA#1 Channel #76

249

DW1_CH_STRUCT77_CH

0x40299340

0x00000040 P-DMA#1 Channel #77

250

DW1_CH_STRUCT78_CH

0x40299380

0x00000040 P-DMA#1 Channel #78

251

DW1_CH_STRUCT79_CH

0x402993C0

0x00000040 P-DMA#1 Channel #79

252

DW1_CH_STRUCT80_CH

0x40299400

0x00000040 P-DMA#1 Channel #80

253

DW1_CH_STRUCT81_CH

0x40299440

0x00000040 P-DMA#1 Channel #81

254

DW1_CH_STRUCT82_CH

0x40299480

0x00000040 P-DMA#1 Channel #82

255

DW1_CH_STRUCT83_CH

0x402994C0

0x00000040 P-DMA#1 Channel #83

256

DMAC_TOP

0x402A0000

0x00000010 M-DMA#0 main

257

DMAC_CH0_CH

0x402A1000

0x00000100 M-DMA#0 Channel #0

258

DMAC_CH1_CH

0x402A1100

0x00000100 M-DMA#0 Channel #1

259

DMAC_CH2_CH

0x402A1200

0x00000100 M-DMA#0 Channel #2

260

DMAC_CH3_CH

0x402A1300

0x00000100 M-DMA#0 Channel #3

261

DMAC_CH4_CH

0x402A1400

0x00000100 M-DMA#0 Channel #4

262

DMAC_CH5_CH

0x402A1500

0x00000100 M-DMA#0 Channel #5

Table 22-1

PPU fixed structure pairs (continued)

Pair

No.

PPU Fixed Structure Pair

Address

Size

Description

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