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CYT4DNJBJS датащи(PDF) 1 Page - Infineon Technologies AG |
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CYT4DNJBJS датащи(HTML) 1 Page - Infineon Technologies AG |
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1 / 209 page ![]() Datasheet Please read the Important Notice and Warnings at the end of this document 002-24601 Rev. *I www.infineon.com page 1 2023-02-14 CYT4DN TRAVEO™ T2G 32-bit Automotive MCU Based on Arm® Cortex®-M7 dual General description CYT4DN is a family of TRAVEO™ T2G microcontrollers targeted at automotive systems such as instrument clusters and Head-Up Displays (HUD). CYT4DN has a 2D Graphics engine, Sound Processing, two Arm® Cortex®-M7 CPUs for primary processing, and an Arm® Cortex®-M0+ CPU for peripheral and security processing. These devices contain embedded peripherals supporting controller area network with flexible data rate (CAN FD), local interconnect network (LIN), clock extension peripheral interface (CXPI), and Gigabit Ethernet. TRAVEO™ T2G devices are manufactured on an advanced 40-nm process. CYT4DN incorporates a low-power flash memory, multiple high-performance analog and digital peripherals, and enables the creation of a secure computing platform. Features • Graphics subsystem - Supports 2D and 2.5D (perspective warping, 3D effects) graphics rendering - Up to 30-bit color resolution (RGB) - 4096 KB of embedded video RAM memory (VRAM) - Up to two video output interfaces supporting two displays from • Parallel RGB (max display size: 1600 × 600 at 80 MHz) • FPD-link single (max display size: 1920 × 720 at 110 MHz) • FPD-link dual (max display size: 2880 × 1080 at 220 MHz) - One Capture engine for video input processing for ITU 656 or parallel RGB/YUV or MIPI CSI-2 input • ITU656 (standard camera capture: up to 800 × 480) • RGB (max capture size 1600 × 600 at 80 MHz) or • Two-/four-lane MIPI CSI-2 interface (max capture size: 1920 × 720 for two lanes at 110 MHz, 2880 × 1080 for four lanes at 220 MHz) - Display warping on-the-fly for HUD applications - Direct video feed through from capture to display interface with graphics overlay - Composition engine for scene composition from display layers - Display engine for video timing generation and display functions - Drawing engine for acceleration of vector graphics rendering - Command sequencer for setup and control of the rendering process - Supports graphics rendering without frame buffers (on-the-fly to both displays) - Dual-channel FPD-Link interface for up to Wide-HD resolution video output -JPEG Decoder • Decodes JPEG images of various formats into pixel data with conformance to a subset of standard ISO/IEC10918-1 • Color spaces supporting RGB/YUV/Grayscale • Supports YUV sub-sampling 4:4:4/4:2:2/4:1:1/4:2:0 • Image size between 1×1 to 16384×16384 pixels • Sound subsystem - Four time-division multiplexing (TDM) interfaces - Two pulse-code modulation-pulse width modulation (PCM-PWM) interfaces - Up to five sound generator (SG) interfaces - Two PCM Audio stream mixers with five input streams - One audio digital-to-analog converter (DAC) |
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