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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CYT4DNJBJS датащи(PDF) 76 Page - Infineon Technologies AG |
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CYT4DNJBJS датащи(HTML) 76 Page - Infineon Technologies AG |
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76 / 209 page  Datasheet 76 002-24601 Rev. *I 2023-02-14 TRAVEO™ T2G 32-bit Automotive MCU Based on Arm® Cortex®-M7 dual Peripheral protection unit fixed structure pairs 22 Peripheral protection unit fixed structure pairs Protection pair is a pair PPU structures, a master, and a slave structure. The master structure protects the slave structure, and the slave structure protects resources such as peripheral registers, or the peripheral itself. Refer to Table 6-1 for the FX PPU Base address. Table 22-1 PPU fixed structure pairs Pair No. PPU Fixed Structure Pair Address Size Description 0 PERI_MAIN 0x40000200 0x00000040 Peripheral Interconnect main 1 PERI_SECURE 0x40002000 0x00000004 Peripheral interconnect secure 2 PERI_GR0_GROUP 0x40004010 0x00000004 Peripheral Group #0 main 3 PERI_GR1_GROUP 0x40004050 0x00000004 Peripheral Group #1 main 4 PERI_GR2_GROUP 0x40004090 0x00000004 Peripheral Group #2 main 5 PERI_GR3_GROUP 0x400040C0 0x00000020 Peripheral Group #3 main 6 PERI_GR4_GROUP 0x40004100 0x00000020 Peripheral Group #4 main 7 PERI_GR5_GROUP 0x40004140 0x00000020 Peripheral Group #5 main 8 PERI_GR6_GROUP 0x40004180 0x00000020 Peripheral Group #6 main 9 PERI_GR8_GROUP 0x40004200 0x00000020 Peripheral Group #8 main 10 PERI_GR9_GROUP 0x40004240 0x00000020 Peripheral Group #9 main 11 PERI_GR10_GROUP 0x40004280 0x00000020 Peripheral Group #10 main 12 PERI_GR0_BOOT 0x40004020 0x00000004 Peripheral Group #0 boot 13 PERI_GR1_BOOT 0x40004060 0x00000004 Peripheral Group #1 boot 14 PERI_GR2_BOOT 0x400040A0 0x00000004 Peripheral Group #2 boot 15 PERI_GR3_BOOT 0x400040E0 0x00000004 Peripheral Group #3 boot 16 PERI_GR4_BOOT 0x40004120 0x00000004 Peripheral Group #4 boot 17 PERI_GR5_BOOT 0x40004160 0x00000004 Peripheral Group #5 boot 18 PERI_GR6_BOOT 0x400041A0 0x00000004 Peripheral Group #6 boot 19 PERI_GR8_BOOT 0x40004220 0x00000004 Peripheral Group #8 boot 20 PERI_GR9_BOOT 0x40004260 0x00000004 Peripheral Group #9 boot 21 PERI_GR10_BOOT 0x400042A0 0x00000004 Peripheral Group #10 boot 22 PERI_TR 0x40008000 0x00008000 Peripheral trigger multiplexer 23 PERI_MS_BOOT 0x40030000 0x00001000 Peripheral master slave boot 24 PERI_PCLK_MAIN 0x40040000 0x00004000 Peripheral clock main 25 CRYPTO_MAIN 0x40100000 0x00000400 Crypto main 26 CRYPTO_CRYPTO 0x40101000 0x00000800 Crypto MMIO (Memory Mapped I/O) 27 CRYPTO_BOOT 0x40102000 0x00000100 Crypto boot 28 CRYPTO_KEY0 0x40102100 0x00000004 Crypto Key #0 29 CRYPTO_KEY1 0x40102120 0x00000004 Crypto Key #1 30 CRYPTO_BUF 0x40108000 0x00002000 Crypto buffer 31 CPUSS_CM7_0 0x40200000 0x00000400 CM7_0 CPU core 32 CPUSS_CM7_1 0x40200400 0x00000400 CM7_1 CPU core 33 CPUSS_CM0 0x40201000 0x00001000 CM0+ CPU core 34 CPUSS_BOOT[44] 0x40202000 0x00000200 CPUSS boot 35 CPUSS_CM0_INT 0x40208000 0x00001000 CPUSS CM0+ interrupts 36 CPUSS_CM7_0_INT 0x4020A000 0x00001000 CPUSS CM7_0 interrupts 37 CPUSS_CM7_1_INT 0x4020C000 0x00001000 CPUSS CM7_1 interrupts Note 44.Fixed PPU is configured inside the Boot and user is not allowed to change the attributes of this PPU. |
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