CYT4DNJBJS datasheet(20/209 Pages) INFINEON

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Datasheet

002-24601 Rev. *I

2023-02-14

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M7 dual

Functional description

peripherals. The trigger multiplexer is used to route triggers from a source peripheral to a destination. Triggers

provide active logic functionality and are typically supported in Active mode.

3.4

Graphics

CYT4DN supports one instance of the graphics subsystem which includes 4096 KB of embedded Video RAM, a 2D

graphics core and interfaces for video input and output processing.

CYT4DN supports 4-lane MIPI CSI-2 interface for up to Wide-HD resolution video inputs and dual channel FPD-link

interface for up to Wide-HD resolution video output. The 2D graphics core supports a BLock Image Transfer (BLIT)

engine for faster graphics rendering to memory or on-the-fly to display, a drawing engine for acceleration of

vector graphics rendering and a command sequencer for setup and control of the rendering process. The video

I/O supports a composition engine for scene composition from display layers, a display engine for video timing

generation, and display functions and a capture engine for video input processing. The device also supports

perspective correction for 3D effects ("2.5D"). One layer can be warped on-the-fly, e.g., for head-up displays. It

includes a JPEG decoder, which decodes JPEG images of various formats into pixel data with conformance to a

subset of ISO/IEC10918-1 (JPEG Part 1). It also supports RGB/YUV/Grayscale color space.

3.5

I/Os

CYT4DN has up to 168 programmable I/Os.

The I/Os are organized as logical entities called ports, which are a maximum of 8 bits wide. During power-on, and

reset, the I/Os are forced to the High-Z state. During the Hibernate mode, I/Os are frozen.

Every I/O can generate an interrupt (if enabled) and each port has an interrupt request (IRQ) and interrupt service

routine (ISR) associated with it.

I/O port power source mapping is listed in Table 3-4. The associated supply determines the VOH, VOL, VIH, and VIL

levels when configured for CMOS and Automotive thresholds.

All I/Os support the following programmable drive modes:

• High impedance

•Resistive pull-up

•Resistive pull-down

• Open drain with strong pull-down

• Open drain with strong pull-up

• Strong pull-up or pull-down

• Weak pull-up or pull-down

CYT4DN has six types of programmable GPIOs: GPIO Standard, GPIO Enhanced, GPIO SMC, HSIO Standard, HSIO

Standard with low-noise, HSIO Enhanced, HSIO Enhanced Differential. Only GPIO_STD, GPIO_ENH, and

GPIO_SMC have the capability to wakeup the device from DeepSleep mode. All these I/Os have GPIO input/output

functionality, HSIO_ENH_PDIFF I/Os (P24, P27) have limitations in single ended mode[18].

Table 3-4

I/O port power source

Supply pins

Ports

VDDD[16]

VDDIO_GPIO_0[16]

P0, P2, P3

VDDIO_GPIO_1[16]

P4, P5, P6

VDDIO_GPIO_2[16]

P7, P8, P29

VDDIO_SMC[16]

P9, P11, P12

VDDIO_HSIO

P13, P14, P15, P16, P17, P18, P19, P20, P21, P30

VDDIO_SMIF

P23, P24, P25, P26, P27, P28

Note

16.Ensure that VDDD ≥ VDDIO_GPIO_2 ≥ VDDIO_GPIO_1. Ensure that VDDD is turned on before VDDIO_GPIO_1, and VDDIO_GPIO_1 is turned on before

VDDIO_GPIO_2, or all at the same time. Also ensure VDDIO_GPIO_2 ≥ VDDA_ADC and VDDIO_SMC ≥ VDDA_ADC to avoid increased leakage.

Operating the mentioned supplies within the same voltage range (i.e. within 2.7V-3.6 V, respectively within 4.5 V-5.5 V) fulfills being

“equal”.

17.Refer to the device Architecture TRM for more details on the I/O configuration.

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