CYT4DNJBJS datasheet(29/209 Pages) INFINEON

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Datasheet

002-24601 Rev. *I

2023-02-14

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M7 dual

CYT4DN CPU start-up sequence

8CYT4DN CPU start-up sequence

The start-up sequence is described in the following steps:

1. System Reset (@0x0000 0000)

2. CM0+ executes ROM boot (@0x0000 0004)

i. Applies trims

ii. Applies Debug Access port (DAP) access restrictions and system protection from eFuse and supervisory

flash

iii.Authenticates flash boot (only in SECURE life-cycle stage) and transfers control to it

3. CM0+ executes flash boot (from Supervisory flash @0x1700 2000)

i. Debug pins are configured as per the SWD/JTAG spec[23]

ii. Sets CM0+ vector offset register (CM0_VTOR part of the Arm® system space) to the beginning of flash

(@0x1000 0000)

iii.CM0+ branches to its Reset handler

4. CM0+ starts execution

i. Moves CM0+ vector table to SRAM (updates CM0+ vector table base)

i. Sets up wait states for different memory subsystems

i. Sets up root clocks, enable core external supply (PMIC), graphics subsystem etc.

i. Sets clocks for CM7_0 (CLK_HF1) and CM7_1 (CLK_HF2)

ii. Sets CM7_0 (CM7_0_VECTOR_TABLE_BASE @0x4020 0200) and CM7_1 (CM7_1_VECTOR_TABLE_BASE

@0x4020 0600) vector tables to the respective locations, also and mentioned in flash (specified in the linker

definition file)

iii.Enables the power for both the CPU cores CM7_0 and CM7_1

iv.Disables CPU_WAIT so as to be able to be accessed by the debugger

v. Releases CM7_0 and/or CM7_1 from reset

vi.Continues execution of CM0+ user application

5. CM7_0 and/or CM7_1 executes directly from either code-flash or SRAM

i. CM7_0/CM7_1 branches to its Reset handler

ii. Continues execution of the user application

Note

23.Port configuration of SWD/JTAG pins will be changed from the default GPIO mode to support debugging after the boot process, refer

to Table 11-1 for pin assignments.

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