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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CYT4DNJBJS датащи(PDF) 89 Page - Infineon Technologies AG |
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CYT4DNJBJS датащи(HTML) 89 Page - Infineon Technologies AG |
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89 / 209 page  Datasheet 89 002-24601 Rev. *I 2023-02-14 TRAVEO™ T2G 32-bit Automotive MCU Based on Arm® Cortex®-M7 dual Peripheral protection unit fixed structure pairs 584 VIDEOSS0_DSPCFG0_FRAMEGEN0 0x40AA2000 0x00000400 VIDEOSS#0 Display Engine#0 Frame Generator#0 585 VIDEOSS0_DSPCOL0_GAMMACOR0 0x40AA2400 0x00000400 VIDEOSS#0 Display Engine#0 Gamma Correction Unit#0 586 VIDEOSS0_DSPCOL0_DITHER0 0x40AA2800 0x00000400 VIDEOSS#0 Display Engine#0 Dither Unit#0 587 VIDEOSS0_DSPIFC0_TCON0 0x40AA3000 0x00000800 VIDEOSS#0 Display Engine#0 Timing Controller#0 588 VIDEOSS0_DSPCFG1_DISENGCFG1 0x40AA4000 0x00000400 VIDEOSS#0 Display Engine#1 Configuration 589 VIDEOSS0_DSPMON1_SIG1 0x40AA5000 0x00000400 VIDEOSS#0 Display Engine#1 Signature Unit#1 590 VIDEOSS0_DSPCFG1_FRAMEGEN1 0x40AA6000 0x00000400 VIDEOSS#0 Display Engine#1 Frame Generator 591 VIDEOSS0_DSPCOL1_GAMMACOR1 0x40AA6400 0x00000400 VIDEOSS#0 Display Engine#1 Gamma Correction Unit#1 592 VIDEOSS0_DSPCOL1_DITHER1 0x40AA6800 0x00000400 VIDEOSS#0 Display Engine#1 Dither Unit#1 593 VIDEOSS0_DSPIFC1_TCON1 0x40AA7000 0x00000800 VIDEOSS#0 Display Engine#1 Timing Controller#1 594 VIDEOSS0_DSPIFC0_FPDLINK0 0x40AC0000 0x00000400 VIDEOSS#0 Display interface0 FPD-Link#0 595 VIDEOSS0_DSPIFC1_FPDLINK1 0x40AC8000 0x00000400 VIDEOSS#0 Display interface0 FPD-Link#1 596 VIDEOSS0_MIPICSI0_MIPICSI_STRUCT_MIPIC- SI_WRAP_MAIN 0x40AD0000 0x00000100 VIDEOSS#0 MIPICSI#0 D-PHY wrapper configuration and status 597 VIDEOSS0_MIPICSI0_MIPICSI_STRUCT_MIPIC- SI_CORE_3PIP 0x40AD0200 0x00000080 VIDEOSS#0 MIPICSI#0 RX Core through APB interface 598 VIDEOSS0_VRPU_MAIN 0x40AF0000 0x00000080 VIDEOSS#0 VRPU Configuration 599 VIDEOSS0_GFX_MPU_RD0_MAIN 0x40AF4000 0x00000004 VIDEOSS#0 MPU Configuration for Read Masters 600 VIDEOSS0_GFX_MPU_RD1_MAIN 0x40AF4400 0x00000004 VIDEOSS#0 MPU Configuration for Read Masters 601 VIDEOSS0_GFX_MPU_RD2_MAIN 0x40AF4800 0x00000004 VIDEOSS#0 MPU Configuration for Read Masters 602 VIDEOSS0_GFX_MPU_RD3_MAIN 0x40AF4C00 0x00000004 VIDEOSS#0 MPU Configuration for Read Masters 603 VIDEOSS0_GFX_MPU_RD4_MAIN 0x40AF5000 0x00000004 VIDEOSS#0 MPU Configuration for Read Masters 604 VIDEOSS0_GFX_MPU_RD5_MAIN 0x40AF5400 0x00000004 VIDEOSS#0 MPU Configuration for Read Masters 605 VIDEOSS0_GFX_MPU_RD6_MAIN 0x40AF5800 0x00000004 VIDEOSS#0 MPU Configuration for Read Masters 606 VIDEOSS0_GFX_MPU_RD7_MAIN 0x40AF5C00 0x00000004 VIDEOSS#0 MPU Configuration for Read Masters 607 VIDEOSS0_GFX_MPU_RD8_MAIN 0x40AF6000 0x00000004 VIDEOSS#0 MPU Configuration for Read Masters 608 VIDEOSS0_GFX_MPU_RD9_MAIN 0x40AF6400 0x00000004 VIDEOSS#0 MPU Configuration for Read Masters 609 VIDEOSS0_GFX_MPU_RD10_MAIN 0x40AF6800 0x00000004 VIDEOSS#0 MPU Configuration for Read Masters 610 VIDEOSS0_GFX_MPU_RD11_MAIN 0x40AF6C00 0x00000004 VIDEOSS#0 MPU Configuration for Read Masters 611 VIDEOSS0_GFX_MPU_RD12_MAIN 0x40AF7000 0x00000004 VIDEOSS#0 MPU Configuration for Read Masters 612 VIDEOSS0_GFX_MPU_RD13_MAIN 0x40AF7400 0x00000004 VIDEOSS#0 MPU Configuration for Read Masters 613 VIDEOSS0_GFX_MPU_RD14_MAIN 0x40AF7800 0x00000004 VIDEOSS#0 MPU Configuration for Read Masters 614 VIDEOSS0_GFX_MPU_RD15_MAIN 0x40AF7C00 0x00000004 VIDEOSS#0 MPU Configuration for Read Masters 615 VIDEOSS0_GFX_MPU_WR0_MAIN 0x40AF8000 0x00000004 VIDEOSS#0 MPU Configuration for Write Masters 616 VIDEOSS0_GFX_MPU_WR1_MAIN 0x40AF8400 0x00000004 VIDEOSS#0 MPU Configuration for Write Masters 617 VIDEOSS0_GFX_MPU_WR2_MAIN 0x40AF8800 0x00000004 VIDEOSS#0 MPU Configuration for Write Masters 618 VIDEOSS0_GFX_MPU_WR3_MAIN 0x40AF8C00 0x00000004 VIDEOSS#0 MPU Configuration for Write Masters 619 VIDEOSS0_GFX_MPU_WR4_MAIN 0x40AF9000 0x00000004 VIDEOSS#0 MPU Configuration for Write Masters 620 VIDEOSS0_GFX_MPU_WR5_MAIN 0x40AF9400 0x00000004 VIDEOSS#0 MPU Configuration for Write Masters 621 VIDEOSS0_GFX_MPU_WR6_MAIN 0x40AF9800 0x00000004 VIDEOSS#0 MPU Configuration for Write Masters 622 VIDEOSS0_GFX_MPU_WR7_MAIN 0x40AF9C00 0x00000004 VIDEOSS#0 MPU Configuration for Write Masters 623 VIDEOSS0_GFX_MPU_WR8_MAIN 0x40AFA000 0x00000004 VIDEOSS#0 MPU Configuration for Write Masters 624 VIDEOSS0_GFX_MPU_WR9_MAIN 0x40AFA400 0x00000004 VIDEOSS#0 MPU Configuration for Write Masters 625 VIDEOSS0_GFX_MPU_WR10_MAIN 0x40AFA800 0x00000004 VIDEOSS#0 MPU Configuration for Write Masters 626 VIDEOSS0_GFX_MPU_WR11_MAIN 0x40AFAC00 0x00000004 VIDEOSS#0 MPU Configuration for Write Masters 627 VIDEOSS0_GFX_MPU_WR12_MAIN 0x40AFB000 0x00000004 VIDEOSS#0 MPU Configuration for Write Masters Table 22-1 PPU fixed structure pairs (continued) Pair No. PPU Fixed Structure Pair Address Size Description |
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