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CYT4DNJBJS датащи(PDF) 5 Page - Infineon Technologies AG |
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CYT4DNJBJS датащи(HTML) 5 Page - Infineon Technologies AG |
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5 / 209 page ![]() Datasheet 5 002-24601 Rev. *I 2023-02-14 TRAVEO™ T2G 32-bit Automotive MCU Based on Arm® Cortex®-M7 dual Table of contents Table of contents General description ...........................................................................................................................1 Features ...........................................................................................................................................1 Table of contents...............................................................................................................................5 1 Features list ...................................................................................................................................6 2 Blocks and functionality..................................................................................................................9 Block diagram...................................................................................................................................9 3 Functional description ..................................................................................................................10 3.1 CPU subsystem .....................................................................................................................................................10 3.2 System resources..................................................................................................................................................11 3.3 Peripherals ............................................................................................................................................................15 3.4 Graphics.................................................................................................................................................................19 3.5 I/Os.........................................................................................................................................................................19 4 CYT4DN address map ....................................................................................................................21 5 Flash base address map.................................................................................................................23 6 Peripheral I/O map........................................................................................................................24 7 CYT4DN clock diagram ..................................................................................................................27 8 CYT4DN CPU start-up sequence......................................................................................................28 9 Pin assignment .............................................................................................................................29 10 High-speed I/O matrix connections...............................................................................................30 11 Package pin list and alternate functions .......................................................................................31 12 Power pin assignments................................................................................................................36 13 Alternate function pin assignments ..............................................................................................37 13.1 Pin function description .....................................................................................................................................44 14 Interrupts and wake-up assignments............................................................................................47 15 Core interrupt types....................................................................................................................57 16 Trigger multiplexer .....................................................................................................................58 17 Triggers group inputs ..................................................................................................................60 18 Triggers group outputs................................................................................................................64 19 Triggers one-to-one.....................................................................................................................65 20 Peripheral clocks ........................................................................................................................68 21 Faults.........................................................................................................................................71 22 Peripheral protection unit fixed structure pairs.............................................................................75 23 Bus masters................................................................................................................................90 24 Miscellaneous configuration ........................................................................................................91 25 Development support..................................................................................................................93 25.1 Documentation ...................................................................................................................................................93 25.2 Tools ....................................................................................................................................................................93 26 Electrical specifications...............................................................................................................94 26.1 Absolute maximum ratings ................................................................................................................................94 26.2 Device-level specifications ...............................................................................................................................100 26.3 Reset specifications ..........................................................................................................................................108 26.4 I/O specifications ..............................................................................................................................................109 26.5 Analog peripherals............................................................................................................................................120 26.6 AC specifications...............................................................................................................................................125 26.7 Digital peripherals.............................................................................................................................................125 26.8 Memory..............................................................................................................................................................139 26.9 System resources..............................................................................................................................................141 26.10 Clock specifications ........................................................................................................................................151 26.11 Ethernet specifications...................................................................................................................................160 26.12 Sound subsystem specifications....................................................................................................................165 26.13 CXPI specifications..........................................................................................................................................170 |
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