CYT4DNJBJS datasheet(7/209 Pages) INFINEON

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Datasheet

002-24601 Rev. *I

2023-02-14

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M7 dual

Features list

1Features list

Table 1-1

CYT4DN feature list

Features

Packages

327-BGA

CPU

Core

Two 32-bit Arm

® Cortex®-M7 CPUs and a 32-bit Arm® Cortex®-M0+ CPU

Functional safety

ASIL-B

Operation voltage for GPIO_STD, GPIO_ENH

2.7 V to 5.5 V

Operation voltage for GPIO_SMC

2.7 V to 5.5 V

Operation voltage for HSIO_STD/HSIO_STDLN

3.0 V to 3.6 V

Operation voltage for HSIO_ENH

1.7 V to 2.0 V

Operation Voltage for HSIO_ENH_PDIFF

1.7 V to 2.0 V

Core voltage VCCD

1.09 V to 1.21 V

Operation frequency

Arm

® Cortex®-M7 320 MHz (max for each) and Arm® Cortex®-M0+ 100 MHz (max)

MPU, PPU

Supported

FPU

Supports both single (32-bit) and double (64-bit) precision

DSP-MUL/DIV/MAC

Supported by Arm

® Cortex®-M7 CPUs

TCM

64-KB instruction and 64-KB data for each Cortex®-M7 CPU

Memory

Code-flash

6336 KB (6080 KB/Large Sectors + 256 KB/Small Sectors)

Work-flash

128 KB (96 KB/Large Sectors+ 32 KB/Small Sectors)

SRAM (configurable for retention)

640 KB (SRAM0/256 KB + SRAM1/256 KB + SRAM2/128 KB)

ROM

64 KB

Communication Interfaces

CAN0/1 (CAN-FD: Up to 8 Mbps)

4 ch

CAN RAM

16 KB per instance (2 ch), 32 KB in total

Serial communication block (SCB)

12 ch

LIN0

2 ch

CXPI controller

2 ch

Ethernet MAC

1 ch × 10/100/1000

Memory Interfaces

SMIF (Single SPI / Dual SPI / Quad SPI / Octal SPI / xSPI)

2 ch (HSIO_ENH + HSIO_ENH_PDIFF at 166 MHz)

Timers

RTC

1 ch

TCPWM (16-bit)

38 ch

TCPWM (16-bit) Motor Control

12 ch (Equivalent to 6 ch SMC with ZPD and slew rate control)

TCPWM (32-bit)

32 ch

External Interrupts

168

Analog

12-bit, 1 Msps SAR ADC

1 Unit (SAR0, 32 logical channels)

48 external channels

6 ch for Internal sampling

Security

Flash Security (program/work read protection)

Supported

Flash Chip erase enable

Configurable

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