CYT4DNJBJS datasheet(61/209 Pages) INFINEON

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Datasheet

002-24601 Rev. *I

2023-02-14

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M7 dual

Triggers group inputs

Table 17-1

Trigger inputs

Input

Trigger Label (TRIG_LABEL)

Description

MUX Group 0: P-DMA0_0_15 trigger multiplexer

1:32

PDMA0_TR_OUT[0:31]

Allow P-DMA0 to chain to itself. Channels 0 - 32 are general purpose channels

available for chaining

33:48

PDMA1_TR_OUT[0:15]

Cross connections from P-DMA1 to P-DMA0, Channels 0-15 are used

49:56

MDMA_TR_OUT[0:7]

Cross connections from M-DMA0 to P-DMA0

57:58

CAN0_TT_TR_OUT[0:1]

CAN0 TT Sync Outputs

59:60

CAN1_TT_TR_OUT[0:1]

CAN1 TT Sync Outputs

61:84

HSIOM_IO_INPUT[0:23]

I/O Inputs

85:88

FAULT_TR_OUT[0:3]

Fault events

MUX Group 1: P-DMA0_16_31 trigger multiplexer

1:38

TCPWM0_16_TR_OUT0[0:37]

16-bit TCPWM0 counters

39:50

TCPWM0_16M_TR_OUT0[0:11]

16-bit Motor enhanced TCPWM0 counters

51:82

TCPWM0_32_TR_OUT0[0:31]

32-bit TCPWM0 counters

83:84

PASS_GEN_TR_OUT[0:1]

PASS0 SAR events

85:86

CTI_TR_OUT[0:1]

Trace events

87:90

EVTGEN_TR_OUT[0:3]

Event generator triggers

MUX Group 2: P-DMA1_0_15 trigger multiplexer

1:16

PDMA1_TR_OUT[0:15]

Allow P-DMA1 to chain to itself. Channels 0 - 15 are dedicated for chaining

17:48

PDMA0_TR_OUT[0:31]

Cross connections from P-DMA0 to P-DMA1, channels 0-31 are used.

49:72

HSIOM_IO_INPUT[24:47]

I/O Inputs

MUX Group 3: M-DMA0 trigger multiplexer

1:8

TCPWM0_16_TR_OUT0[0:7]

16-bit TCPWM0 counters

9:16

TCPWM0_32_TR_OUT0[0:7]

32-bit TCPWM0 counters

17:20

AXIDMA_TR_OUT[0:3]

AXI M-DMA1 triggers

MUX Group 4: TCPWM0 Trigger multiplexer

1:32

PDMA0_TR_OUT[0:31]

General purpose P-DMA0 triggers

33:48

PDMA1_TR_OUT[0:15]

General purpose P-DMA1 triggers

49:56

MDMA_TR_OUT[0:7]

AHB M-DMA0 triggers

57:94

TCPWM0_16_TR_OUT0[0:37]

16-bit TCPWM0 counters

95:106

TCPWM0_16M_TR_OUT0[0:11]

16-bit Motor enhanced TCPWM0 counters

107:138

TCPWM0_32_TR_OUT0[0:31]

32-bit TCPWM0 counters

139

SMIF0_TX_TR_OUT

SMIF0 TX trigger

140

SMIF0_RX_TR_OUT

SMIF0 RX trigger

141

SMIF1_TX_TR_OUT

SMIF1 TX trigger

142

SMIF1_RX_TR_OUT

SMIF1 RX trigger

143:146

AXIDMA_TR_OUT[0:3]

AXI M-DMA1 triggers

151:154

TDM0_TX_TR_OUT[0:3]

TDM0 TX trigger

155:158

TDM0_RX_TR_OUT[0:3]

TDM0 RX trigger

159:163

SG0_TX_TR_OUT[0:4]

SG0 TX trigger

164:165

PWM0_TX_TR_OUT[0:1]

PWM0 TX trigger

166:170

MIXER0_TR_SRC_REQ_OUT[0:4]

MIXER0 SRC trigger

171

MIXER0_TR_DST_REQ_OUT

MIXER0 DST trigger

172:176

MIXER1_TR_SRC_REQ_OUT[0:4]

MIXER1 SRC trigger

177

MIXER1_TR_DST_REQ_OUT

MIXER1 DST trigger

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