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VSC8504-02 датащи(PDF) 129 Page - Microsemi Corporation

номер детали VSC8504-02
подробное описание детали  Quad-Port 10/100/1000BASE-T PHY with Synchronous Ethernet and QSGMII/SGMII MAC
PDF  131 Pages
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производитель  MICROSEMI [Microsemi Corporation]
домашняя страница  http://www.microsemi.com
Logo MICROSEMI - Microsemi Corporation

VSC8504-02 датащи(HTML) 129 Page - Microsemi Corporation

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Design Considerations
VMDS-10507 VSC8504-02 Datasheet Revision 4.2
118
8.15
Near-end loopback non-functional in protocol transfer
mode
Near-end loopback does not work correctly when the device is configured in protocol transfer mode.
This is a debug feature and does not have any effect on the normal operation of the device.
8.16
Fiber-media CRC counters non-functional in protocol
transfer mode at 10 Mbps and 100 Mbps
Packets received on the media SerDes interface will not be counted correctly in registers 28E3 and 29E3
when the device is configured in protocol transfer mode and operating at 10 Mbps or 100 Mbps speeds.
These counters are used for debugging and there is no effect on the normal operation of the device.
8.17
Fiber-media recovered clock does not squelch based on
link status
To squelch the clock in fiber media mode, code sync status is used instead of link status. This causes the
clock to not be squelched if the device is configured in 1000BASE-X mode with autonegotiation enabled
when the transmit fiber is unplugged.
There is a software workaround for this issue where the device's internal microcontroller monitors link
status and forces the clock off when no link is present.
8.18
1000BASE-X parallel detect mode with Clause 37
autonegotiation enabled
When connected to a forced-mode link partner and attempting autonegotiation, the PHY in 1000BASEX
parallel detect mode requires a minimum 250 ms IDLE stream in order to establish a link. If the PHY port
is programmed with 1000BASE-X parallel detect-enabled (MAC-side register 16E3 bit 13, or media-side
register 23E3 bit 13), then a forced-mode link partner sending traffic with an inter-packet gap less than
250 ms will not allow the local device’s PCS to transition from a link-down to link-up state.
8.19
Anomalous PCS error indications in Energy Efficient
Ethernet mode
When a port is processing traffic with Energy Efficient Ethernet enabled on the link, certain PCS errors
(such as false carriers, spurious start-of-stream detection, and idle errors) and EEE wake errors may
occur. There is no effect on traffic bit error rate for cable lengths up to 75 meters, and minor packet loss
may occur on links longer than 75 meters. Regardless of cable length, some error indications should not
be used while EEE is enabled. These error indications include false carrier interrupts (Interrupt Status
register 26 bit 3), receive error interrupts (Interrupt Status register 26 bit 0), and EEE wake error
interrupts.
Contact Microsemi for a script that needs to be applied during system initialization if EEE will be enabled.
8.20
Long link-up times while in forced 100BASE-TX mode of
operation
While in forced 100BASE-TX operation and attempting to link up, the device may experience abnormally
long link-up times.
This issue can only occur if the Unified API is not used with the device. In those circumstances, the
workaround for this issue is to clear all speed advertisements in the autonegotiation advertisement
registers (register 4, bits 9:5 and register 9, bits 9:8), then toggle the auto-negotiation enable bit of the
mode control register (register 0, bit 12) for a port upon detecting its link is down. Any advertisements
temporarily cleared can then be restored once register 0, bit 12 is cleared.



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