MPF0900AMBA2ES datasheet(152/205 Pages) NXP

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NXP Semiconductors

PF09

Nine-channel power management IC with advanced system safety monitoring

aaa-056082

WD_OK_CNT

WD refresh OK

n = WDOK_FC

WD_OK_CNT

reset after

reaching max

count

WD refresh NOK

FAULT_CNT -1

WD refresh OK

Figure 41. WD_OK counter

The WD_OK counter works together with the WD_OK_FCD[2:0] bits to allow a number of consecutive WD_OK

events to reduce the fault and reset counters by 1.

The WD_OK_FCD[2:0] provides an automatic way to keep the system counters clean as long as the system is

healthy and able to service the PMIC watchdog. This reduces the need of constant housekeeping which could

potentially result in systemic fault conditions where the system can fall into a software loop where it is not able

to move forward and the PMIC is not able to reach the maximum fault count limit, because the MCU clears the

fault counters within the software loop.

The default value for the WD_OK_FCD[2:0] is loaded from OTP at power up via the OTP_WD_OK_FDC[2:0]

bits.

WD_OK_FCD[2:0]

Good WD fault clear

000

Good WD cannot clear faults

001

Every one WD refresh OK

010

Every two WD refresh OK

011

Every three WD refresh OK

100

Every four WD refresh OK

101

Every five WD refresh OK

110

Every six WD refresh OK

111

Every seven WD refresh OK

Table 198. WD_OK events required to reduce the Fault counter by 1

PF09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 16 December 2025

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