MPF0900AMBA2ES datasheet(57/205 Pages) NXP

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NXP Semiconductors

PF09

Nine-channel power management IC with advanced system safety monitoring

aaa-056062

RSTB

PGOOD

(optional)

REG4_PG

REG4

REG3_PG

REG3

REG2_PG

REG2

REG1_PG

REG1

2 ms (max)

recovery

Reg power down

SEQ SLOT 1 SEQ SLOT 2 SEQ SLOT 3

PWRUP fail

PG’s NOK

POWER-UP FAILURE WITH PERSISTENT FAULT CONDITION

Figure 17. Power-up failure with persistent fault condition

After the RSTB is released, an OV/UV or ILIM condition will trigger a fault detection and protection mechanism

as described in section Section 12.6.2.

If a regulator fault occurs after RSTB is released but before the Power-up sequence is finalized, the Power-up

sequence will continue to power up if the fault condition is not enough to start a hard fault, based on the fault

management rules during the SYSTEM ON states.

During the Power-up sequence, the PGOOD pin will be used as an external indicator of an OV/UV failure when

the RSTB is ready to be de-asserted, since the PG_EN bits for all regulators are reset to 1 at power up.

When the OTP_PWRUP_CHK = 1, the RSTB must be set to release at a later slot than any of the voltage

regulators needed by the system before going out of the reset condition. This will allow sufficient time for all

regulators to reach their corresponding regulation point during the power-up sequence and avoid false fault

conditions due to the regulators ramping up too slowly.

When the RSTB pin is intended to be released before all of the switching and LDO regulators, the

OTP_PWRUP_CHK bit should always be set to 0, to prevent the system from generating a power-up failure

event.

When OTP_PWRUP_CHK = 1, if any IO is used as a GPOx, it may be released at any time in the Power-up

sequence, as long as the RSTB does not try to release before there is an actual regulator enabled to check for

a power good condition (system-level configuration).

12.6.5 Fault monitoring during dynamic power up

When operating in dynamic power-up, the PF09 will start monitoring for OV and UV conditions as soon as

the regulator is enabled. If an OV/UV condition is detected while the Power-up sequence is in progress, such

condition will be used as a gating factor to prevent the regulator on the next hierarchical level from turning on

until all regulators enabled previously are in regulation.

When regulators in the next hierarchical level are enabled, the settling timer is restarted to allow the new

regulators to ramp up and reach regulation.

PF09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 16 December 2025

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