MPF0900AMBA2ES datasheet(48/205 Pages) NXP

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NXP Semiconductors

PF09

Nine-channel power management IC with advanced system safety monitoring

corrective action before the PMIC detects a lack of response and proceeds to evaluate the fault conditions as

a hard fault.

12.6.1 Fault counter

The PF09 features a programmable fault counter to avoid fault cycling during system operation.

The device uses the FAULT_MAX_CNT[3:0] bits to set the maximum number of soft faults allowed before the

PMIC detects a cyclic fault condition and generates a hard fault condition.

When the FAULT_MAX_CNT[3:0] = 0x00, the soft fault condition will still be detected but the system will not be

able to generate a system shutdown due to a hard fault.

When the FAULT_MAX_CNT[3:0] is different from 0x00, the PMIC will generate a hard fault when the

FAULT_CNT[3:0] = FAULT_MAX_CNT[3:0].

The default value of the FAULT_MAX_CNT[3:0] bits is set by the OTP_FAULT_MAX_CNT[3:0] bits to ensure

the system starts operation with a valid configuration. However, the MCU is allowed to change the value of the

FAULT_MAX_CNT[3:0] bits at any time to adjust the PMIC reaction to the needs of the application.

If the FAULT_CNT[3:0] < FAULT_MAX_CNT[3:0], the device will initiate the corresponding fault protection

mechanism based on the type of fault and the configuration in the functional register bits.

OV, UV, and ILIM faults in the voltage regulators and external VMON will increased the fault counter only if the

fault is not bypassed, and no other persistent OV, UV, or ILIM fault is currently present on any of the system

regulators or external VMON blocks.

FCCU and ERRMON faults will increase the FAULT_CNT[3:0] only if the FS0B pin transitions from high to low,

to prevent multiple fault detections from a fault condition that hasn’t been properly cleared out by the MCU.

The MCU is expected to implement a fault acknowledgement routine to read the faults and clear the fault

counter when it has taken proper action, and the system is ready to resume normal operation. By implementing

such a routine, the system ensures that no fault conditions are stacking up in the fault counter and prevents a

random condition from generating a hard fault right away.

The fault counter can be cleared manually by writing the FAULT_CNT[3:0] = 0x00 via an I2C command, or

automatically by allowing the watchdog interface to reduce the counter gradually when a number of consecutive

good watchdog refreshes have been performed. Refer to Section 14.4.3 for more details on using the watchdog

interface to decrease the fault counter automatically.

12.6.2 System regulators and external VMON fault management

The switching regulators and LDOs are provided with internal voltage monitors to detect overvoltage (OV)

and undervoltage (UV) conditions during the Power-up sequence and the SYSTEM ON states. Additionally,

overcurrents are detected and protected during the system-on states by the ILIM mechanism.

Note that the voltage monitoring is only able to detect and protect against OV/UV conditions in the monitored

STANDBY state (OTP_LP_STBY = 0). If the device is configured to go into the low-power STANDBY state,

all monitoring blocks will be disabled to allow the lowest quiescent current possible with the assumption that

STANDBY is considered a safe state in which the system will not perform critical activity, therefore no safety

monitoring is required.

Refer to Section 13.3 for detailed operation and configuration of the OV/UV monitoring blocks.

Fault reaction of the system regulators and external voltage monitors can be managed through the dedicated

fault management bit provided for each block.

PF09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 16 December 2025

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