MPF0900AMBA2ES datasheet(44/205 Pages) NXP

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NXP Semiconductors

PF09

Nine-channel power management IC with advanced system safety monitoring

OTP_EWARN_TIME[1:0]

EWARN delay time

100 μs

5 ms

20 ms

50 ms

Table 41. EWARN delay time

12.4.4 Power-down sequencing

The PF09 provides a highly flexible scheme to control the power-down sequence. It relies on the configuration

of the _SEQ[7:0] bits and the SEQ_TBASE[1:0] bits to set the order in which the voltage regulators, GPIO, or

voltage monitors will be sequenced down during a power-down event.

The values of the _SEQ[7:0] and SEQ_TBASE[1:0] bits are set by default, as defined by the Power-up

sequence in the OTP registers. The regulators, GPIO, and VMON, will perform the power-down sequence

in the reverse order with respect to the Power-up sequence, that is, channels with the higher slot in their

corresponding _SEQ[7:0] bits will be disabled first, and those with the lower slot will be disabled last.

Channels whose _SEQ[7:0] bits are set to 0x00 will be disabled first, before the sequenced slots are disabled.

In scenarios where the system requires a different power-down sequencing, the MCU can change the values

in the _SEQ[7:0] and SEQ_TBASE[1:0] bits during the SYSTEM ON states to ensure the PMIC will sequence

down in the next power cycle following the new values.

When the device passes through any of the OFF States, the SEQ_TBASE[1:0] and _SEQ[7:0] bits are reloaded

with the default values in the OTP registers before it starts the next power-up sequence, to ensure the system is

able to power up with a valid Power-up sequence.

If all of the sequence bits are set to _SEQ[7:0] = 0x00, all the system regulators, VMONx, GPOx, and RSTB

pins will be turned off at once when the power-down sequencer is invoked.

12.4.4.1 VAON power-down control

The behavior of the VAON during a power-down sequence is dependent on the mode of operation of this LDO.

When the VAON is configured as a “system regulator”, it will be included in the Power-down sequence based on

the _SEQ[7:0] bits, as described in the previous section.

When the VAON is configured as an “always-on regulator”, the output will remain enabled during the power-

down sequence, and during the OFF states, to ensure the system doesn’t lose this voltage during the full power

cycle.

If the power down is started by an OV/UV condition on the VAON supply operating as an always-on regulator,

the reaction of the output will depend on the fault mode configuration of the VAON regulator. Refer to

Section 12.6.3 for detailed description of the VAON behavior in this particular scenario.

If the device reaches the Deep Fail-safe state (DFS), the VAON output will be disabled to protect the system,

and default operation will be recovered once the device exit the DFS state and the OTP fuses are reloaded.

12.4.4.2 Power-down delay

A programable delay after the power-down sequence can be set using the PD_SEQ_DLY[2:0] bits.

PF09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 16 December 2025

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