MPF0900AMBA2ES datasheet(42/205 Pages) NXP

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NXP Semiconductors

PF09

Nine-channel power management IC with advanced system safety monitoring

If VMON1 or VMON2 are enabled when a soft reset occurs, the voltage monitoring will be masked during the

soft reset, and the VMON mask timer will be started. The voltage monitoring channel will be unmasked after the

VMON mask timer VMONx_TMASK[1:0] has expired, and the system will start monitoring for OV/UV conditions

at the default voltage level.

The RSTB can be programmed to remain released or assert temporarily to generate a physical reset condition

for the MCU. The RSTB_SOFTRST[1:0] bits are provided to program the behavior of the RSTB pin upon a soft

reset condition.

RSTB_SOFTRST[1:0]

RSTB pulse on soft reset

No RSTB assertion

Assert RSTB for 100 μs

Assert RSTB for 500 μs

Assert RSTB for 1000 μs

Table 40. RSTB pulse on soft reset

The OTP_RSTB_SOFTRST[1:0] is provided to set the default value of the RSTB_SOFTRST[1:0] bits.

In applications where the watchdog timer is enabled at power-up, if the RSTB pin is programmed to assert

temporarily during a soft reset, the device will stop the watchdog timer during the reset event and it will

restart with the default configuration after the RSTB pin is released, to allow the system to perform the initial

configuration and start servicing the watchdog again.

When a soft reset event is present, the device will clear all the interrupt latches before reloading the default

values into the functional register. This allows the device to assert the INTB pin when the PWRUP_I is latched,

when all voltages finished transitioning to the default values.

12.4.2.3 Reset counter

When the device has started a reset event, the value in the RESET_CNT[3:0] bits will be increased. If the

RESET_CNT[3:0] reaches the maximum number of reset events allowed by the RESET_MAX[3:0] bits, the

system will detect a cyclic reset failure and it will perform a fault power-down sequence and proceed to the Fail-

safe transition.

The MCU is expected to clear the RESET_CNT[3:0] when it is able to regain proper operation after the reset

condition. The RESET_CNT[3:0] will be reset automatically when the state machine enters the LPOFF state, to

ensure the system starts with a clean count on a fresh power-up event. The RESET_MAX[3:0] is loaded with

the values on the OTP_RESET_MAX[3:0] bits.

PF09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 16 December 2025

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