MPF0900AMBA2ES datasheet(60/205 Pages) NXP

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NXP Semiconductors

PF09

Nine-channel power management IC with advanced system safety monitoring

12.7.2 Interrupt management

The MCU can be notified of any interrupt event through the INTB pin and the various interrupt registers provided

by the PF09. The INTB pin is a reflection of a logic OR of all the interrupt status bits allowed to control the pin.

Interrupts are reported in two levels on the interrupts registers: At first level, the SYSTEM_INT register provides

information about the interrupt register that originated the interrupt event. At the second level, the remaining

interrupt registers provide the exact source for the interrupt event.

The corresponding SYSTEM_INT bits are set when the INTB pin is asserted by any of the second-level interrupt

bits that have not been masked. Likewise, when the second-level interrupt bit is cleared, the corresponding first-

level interrupt bit on the SYSTEM_INT register is cleared automatically.

System interrupt flag

Source of interrupt

STATUS1_I

Bit is set when interrupt is generated in register:

• STATUS1_INT

STATUS2_I

Bit is set when interrupt is generated in registers:

• STATUS2_INT

• STATUS3_INT

MODE_I

Bit is set when interrupt is generated in register:

• SW_MODE_INT

ILIM_I

Bit is set when interrupt is generated in registers:

• SW_ILIM_INT

• LDO_ILIM_INT

UV_I

Bit is set when interrupt is generated in registers:

• SW_UV_INT

• LDO_UV_INT

OV_I

Bit is set when interrupt is generated in registers:

• SW_OV_INT

• LDO_OV_INT

GPIO_I

Bit is set when interrupt is generated in registers:

• PWRON_INT

• IO_INT

EWARN_I

The EWARN_I is the only interrupt bit in the system without a mask bit, and it will cause the

INTB pin to assert every time a critical fault is causing the device to shut down.

Table 58. System interrupt flags

Whenever an interrupt event occurs, the corresponding interrupt latch bit (_I) will be set, and the system must

write a 1 to the corresponding status bit to clear the interrupt.

Each second-level interrupt is provided with a mask bit to control whether a given interrupt latch bit can assert

the INTB pin low or not. Only the PWRUP_I interrupt is not masked by default, in order to allow the INTB pin to

assert when the power-up sequence is finished.

Faults or conditions with a steady state are provided with a sense bit xxx_S to read the current status of such

conditions. Interrupts generated by transient faults or events do not provide sense bits.

Bit value

Interrupt latch [ _I ]

Interrupt mask [ _M ]

Sense bit [ _S ]

No event present

Asserts INTB (not-masked)

Condition is not present

Event latched

Does not assert INTB (masked)

Condition is currently present

Table 59. Interrupt latch, interrupt mask, and sense bits

PF09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 16 December 2025

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