MPF0900AMBA2ES datasheet(74/205 Pages) NXP

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NXP Semiconductors

PF09

Nine-channel power management IC with advanced system safety monitoring

The operation of the FS0B pin depends on the safety integrity level of the device.

In non-safety devices (QM), the FS0B pin operates in Fault status mode.

In automotive safety devices (ASIL B/C/D), the FS0B pin operates in Active Safe-state mode.

In industrial safety devices (SIL 2) the FS0B pin operates in Active Safe-state mode.

Detailed description of the Active Safe-state mode is provided in section 18.5 FS0B Active Safe State Mode.

12.8.7.1 Fault status mode

In Fault status mode, the FS0B pin can be programmed to assert when a specific fault event is present. The

FS0B fault control bits are provided to allow the FS0B pin to assert when either of the selected fault conditions

is present.

When an FS0B fault control bit is set to 0, the fault event will assert the corresponding fault flag, but it will not be

able to control the FS0B pin.

When an FS0B fault control bit is set to 1, the fault event will assert the corresponding fault flag and also assert

the FS0B pin to report the fault condition to the system.

The FS0B pin will be released when all the system fault flags are cleared, by writing a 1 to the flag. Refer to

section 16.7.1 System Fault Flags for a detailed description of the system fault flags.

FS0B Fault Control

Description

FS0B_DCRC

Allows FS0B to assert on dynamic CRC event

FS0B_DFS

Allows FS0B to assert when entering the DFS state

FS0B_VIN_OV

Allows FS0B to assert on a VIN_OV event

FS0B_XFAIL

Allows FS0B to assert when the XFAILB is asserted externally

FS0B_WD

Allows FS0B to assert when a watchdog event is present

FS0B_XRESET

Allows FS0B to assert when an reset is requested via the XRESET or FCCU

FS0B_SFAULT

Allows FS0B to assert when a soft fault is present

FS0B_HFAULT

Allows FS0B to assert when a hard fault is present:

• Fault timer expired

• FAULT_CNT = FAULT_MAX_CNT

• RESET_CNT = RESET_MAX

• Power up failure

• Thermal shutdown

• The RSTB pin short-to-low detected.

• VIN crossing the UVDET on the Falling edge

Table 74. FS0B Fault control bits

12.8.8 FCCU1 (XRESET mode)

The FCCU1 pin is a programmable input pin in the PF09 to provide monitoring of external fault signals with

various modes of operation. In devices where the FCCU operation is not available, the FCCU1 pin uses the

OTP_FCCU1_MODE[1:0] bits to enable the external reset (XRESET) operation.

OTP_FCCU0_MODE[1:0]

OTP_FCCU1_MODE[1:0]

FCCU1 Operation

Don’t care

No operation

Table 75. FCCU1 pin operation when FCCU block is not available in the system.

PF09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 16 December 2025

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