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MPF0900AMBA2ES датащи(PDF) 96 Page - NXP Semiconductors |
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MPF0900AMBA2ES датащи(HTML) 96 Page - NXP Semiconductors |
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96 / 205 page ![]() NXP Semiconductors PF09 Nine-channel power management IC with advanced system safety monitoring SW1_STBY_MODE[1:0] Mode selection in STANDBY 01 PWM[1] 10 PFM 11 Reserved Table 116. Mode selection in STANDBY...continued [1] PWM selection is only available during the monitored STANDBY state. The regulator will operate in PFM when the device is in the LP_STANDBY state. The default value for the SW1_STBY_MODE[1:0] bits is loaded at power-up from the OTP_SW1_STBY_EN bit. OTP_SW1_STBY_EN SW1 operation in STANDBY 0 OFF 1 PFM Table 117. Default SW1 mode selection during STANDBY When the SW1 regulator changes the mode between the PWM and PFM, The SW1_MODE_I interrupt will be generated when the mode transition is finished. The INTB pin will be asserted if the SW1_MODE interrupt is not masked. The SW1_ILIM[1:0] bits are provided to program the current limit detection in the SW1 regulator. The default current limit is loaded at power up from the OTP_SW1_ILIM[1:0] bits. SW1_ILIM[1:0] Current limit 00 6.0 A 01 4.0 A 10 5.0 A 11 6.0 A Table 118. Current limit selection bits The SW1_PH[2:0] bits are provided to control the phase shift of the switching frequency. The default switching phase is loaded at power up from the OTP_SW1_PH[2:0] bits. SW1_PH[2:0] Phase control 000 45° 001 90° 010 135° 011 180° 100 225° 101 270° 110 315° 111 0° Table 119. SW1 phase shift selection bits 13.2.2.1 3.3 V load switch operation The load switch operation in SW1 is provided to support systems operating from a 3.3 V input supply requiring a 3.3 V gated output capable of being sequenced in the right order during the Power-up sequence. In such PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 1.3 — 16 December 2025 Document feedback 96 / 205 |
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