MPF0900AMBA2ES datasheet(47/205 Pages) NXP

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NXP Semiconductors

PF09

Nine-channel power management IC with advanced system safety monitoring

12.6 Fault management

The PF09 provides a flexible fault management scheme to detect and react to internal and external faults:

• Voltage regulators are monitored internally for overvoltage, undervoltage, and overcurrent.

• Dedicated inputs are used to monitor external supplies for overvoltage and undervoltage.

In devices with safety monitoring, external error monitoring is provided via the XRESET, FCCU, and/or

ERRMON interfaces.

Internal random fault conditions are monitored through the various mechanisms provided by the functional

safety architecture. Refer to Section 14 for detailed descriptions and fault handling of safety-related

mechanisms.

The fault protection mechanisms upon a system regulator fault can be programmed to one or more of the

following reactions:

• Set the corresponding interrupt latch and assert the INTB pin if the interrupt is not masked.

• Disable the failing output if the corresponding _STATE bit is set to 0.

• Start the fault timer, if programmed by the TIMER_FAULT[3:0] bits.

• Assert the PGOOD pin low of the corresponding OV/UV, if fault condition is not bypassed.

• Increase the fault counter, if the OV/UV fault condition is not bypassed.

• Assert the FS0B pin (based on device configuration).

The fault protection mechanisms upon an external VMONx OV/UV fault can be programmed to one or more of

the following reactions:

• Set the corresponding interrupt latch and assert the INTB pin if the interrupt is not masked.

• Start the fault timer if programmed by the TIMER_FAULT[3:0] bits.

• Assert the PGOOD pin low if the corresponding OV/UV if fault condition is not bypassed.

• Increase the fault counter if the OV/UV fault condition is not bypassed.

• Assert the FS0B pin (based on device configuration).

The fault protection mechanisms upon an FCCU fault can be programmed to one or more of the following

reactions:

• Set the corresponding interrupt latch and assert the INTB pin if the interrupt is not masked.

• Assert the FS0B pin.

• Generate a reset condition as defined by the FCCUx_RESET[1:0] bits.

The fault protection mechanisms upon an ERRMON fault can be programmed to one or more of the following

reactions:

• Set the corresponding interrupt latch and assert the INTB pin if the interrupt is not masked.

• Assert the FS0B pin.

• Generate a reset condition as defined by the ERRMON_RESET bit.

Fault conditions are classified based on the severity of their reactions:

• Hard faults: fault conditions that cause the device to start a power-down sequence. It is assumed that such a

fault may limit the ability of the system (MCU) to properly acknowledge and recover from the fault condition,

therefore the PMIC is required to take a definite action to bring the system to a known “good” state to resume

proper operation.

• Soft faults: fault conditions that do not start a power-down sequence. It is assumed such faults do not limit the

ability of the system to acknowledge and try to act upon the fault condition. Soft faults are signalled by one

or more mechanisms, such as the interrupt registers, INTB, FS0B_S or PGOOD pins. The MCU is expected

to listen to any of these signals as defined by the system designer, and the system is expected to perform a

PF09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 16 December 2025

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