MPF0900AMBA2ES datasheet(86/205 Pages) NXP

86 / 205 page

NXP Semiconductors

PF09

Nine-channel power management IC with advanced system safety monitoring

I2C_SECURE_EN

I2C secure write

Disabled

Enabled

Table 103. Enabling I2C secure write

When secure write is enabled, a specific sequence must be followed in order to grant write access on the

corresponding secure register:

1. The MCU sends a command to modify the secure registers

2. The MCU reads a random code generated by the PMIC from the RANDOM_GEN register

3. The MCU must write the correct random code in the RANDOM_CHK register.

If RANDOM_CHK [7:0] matches the value in the RANDOM_GEN[7:0] bits, the device applies the configuration

as requested by the initial command.

If RANDOM_CHK[7:0] is different from RANDOM_GEN[7:0], the device ignores the configuration command and

waits for a new transaction.

In the event the MCU sends any other command instead of providing a value for the RANDOM_CHK register

when the PF09 is expecting a random code confirmation, the device will cancel the ongoing secure write

transaction and perform the new I2C command.

In the event the MCU does not provide a value for the RANDOM_CHK register when the PF09 is expecting a

random code confirmation, the I2C transaction will time out 10 ms After the RANDOM_GEN code is generated,

and the device will be ready for a new transaction.

The following table provides a list of all the bits requiring a secure write protocol when I2C_SECURE_EN = 1.

Bit group

Description

Bit group

Description

System Configuration bits

I2C_SECURE_EN

I2C secure write

STBY_POL

STBY pin polarity

RSTB_SOFTRST

RSTB pulse on soft reset

XRST_MODE

XRESET operating mode

VIN_OV_EN

VIN overvoltage protection

XRST_STBY_EN

XRESET operation in

STANDBY

VIN_OV_SDWN

VIN overvoltage shutdown

XRST_DBNC

XRESET debounce timer

VIN_OV_DBNC

VIN overvoltage debounce

WD_EN

Watchdog counter

OV_DBNC

Regulator OV debounce

WD_DURATION

WD window duration

UV_DBNC

Regulator UV debounce

WD_OK_FCD

Fault counter reduction

FAULT_MAX_CNT

Maximum fault count

WD_NOK_MAX

WD NOK reset limit

TIMER_FAULT

Regulator fault timer

ERRMON_RESET

ERRMON reaction

RESET_MAX

Max reset events

ERRMON_TIME

ERRMON acknowledge time

FCCUx_POL

FCCU0 fault polarity

FCCU1 fault polarity

FCCUx_RPULL_EN

FCCU0 internal pull resistor

FCCU1 internal pull resistor

FCCUx_DBNC

FCCU0 debounce time

FCCU1 debounce time

FCCUx_RESET

FCCU1 reset configuration

FS0B_RELEASE

FS0B release command

VSELECT_EN

LDO2 VSELECT mode

SYS_CMD

System commands

–

Table 104. Bit groups that may require a secure write protocol

PF09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 16 December 2025

Document feedback

86 / 205

MPF0900AMBA2ES датащи(PDF) 86 Page - NXP Semiconductors

MPF0900AMBA2ES датащи(HTML) 86 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL