MPF0900AMBA2ES datasheet(52/205 Pages) NXP

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NXP Semiconductors

PF09

Nine-channel power management IC with advanced system safety monitoring

TIMER_FAULT [3:0]

Fault timer value

1111

Reserved

Table 51. Fault timer...continued

While the fault timer is in progress, the processor is expected to take action to clear the fault condition. For

example, it could reduce its load in the event of a current limit fault, or turn off the regulator in the event of an

overvoltage fault.

If the fault is cleared before the fault timer expires, the state machine will resume normal operation, and the fault

timer will be restarted on the next fault condition.

If the fault does not clear before the timer expires, a hard fault is generated and the device will start a power-

down sequence. Once system regulators are turned off after a hard-fault shutdown, the device will move to the

Fail-safe transition in order to keep track of the number failing events in the system.

When the fault timer is disabled (TIMER_FAULT[3:0] = 0b0000), a persistent fault will not be able to start a

hard-fault condition. The system designer is responsible for planning the proper fault handling strategy suitable

to each specific application.

12.6.3 VAON fault management

12.6.3.1 VAON always-on mode

When the VAON supply is configured as an always-on supply, the fault detection and reaction depends on the

state and the fault mode configuration during the SYSTEM ON states.

In the low-power states, a low-power analog undervoltage monitor is implemented to detect when the VAON

output has gone below the VAON_LP_UV threshold. The low-power voltage monitor is intended to prevent

the system from becoming unresponsive due to a latch-up condition in the VAON domain, and it should not be

considered a safety-related block during the safety analysis of the PMIC.

When the VAON output falls below the VAON_LP_UV threshold during the OFF states, the regulator will

generate a self-reset cycle, applying an internal pulldown resistor for 600 µs to ensure the output voltage is

discharged, in order to ensure the load is able to cross its POR threshold before it proceeds to re-enable the

VAON output.

When the state machine reaches the DBGOFF state, the VAON will be monitored for OV and UV to ensure the

VAON output is in regulation before the power-up sequence can be started.

During the low-power STANDBY state (OTP_LP_STBY = 1) the VAON reaction to an OV/UV condition is

selected via the OTP_VAON_FMODE bit.

When the OTP_VAON_FMODE = 0, the VAON will ignore any OV/UV conditions and no protective reaction will

be available.

When the OTP_VAON_FMODE = 1, the low-power undervoltage monitor will be enabled to allow the system to

detect the VAON falling below the VAON_LP_UV threshold and generate a full PMIC power-down sequence.

In the low-power STANDBY state, the system may not support I2C communication, and most of the monitoring

circuits are disabled, including the system watchdog timer. A temporary loss of the VAON may result in a non-

responsive system. Therefore, when the VAON_LP_UV condition is present, the PF09 will start a full reset

condition, including the VAON supply last in the power-down sequence and applying the power-down delay

after the VAON Is disabled, in order to allow enough time for all rails to be discharged properly before the

system can re-enable the VAON regulator when it reaches the LPOFF state.

During the monitored system-on states (RUN and monitored STANDBY state), the VAON low-power

undervoltage monitor is disabled to allow the system to manage safety-related fault conditions via the

programable OV/UV monitor on VAON.

PF09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 16 December 2025

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