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MPF0900AMBA2ES датащи(PDF) 33 Page - NXP Semiconductors |
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MPF0900AMBA2ES датащи(HTML) 33 Page - NXP Semiconductors |
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33 / 205 page ![]() NXP Semiconductors PF09 Nine-channel power management IC with advanced system safety monitoring VIN aaa-056049 VDIG PWRON Wake-up event VAON XFAILB PWRUP_READY Regulator outputs (enable signals) RSTB PWRON event Final VAON regulation DFS Fuse pre-load + LBIST Fuse load Self test tfirst treg2rstb Only if LBIST enabled tFLoad tLBIST tFLoad tSTEST tBOOT1 Figure 10. PMIC wake-up from DFS The default timing for the external regulators to start up is set via the OTP bits as described in Section 12.3.3. All parameters are specified at TA = -40 °C to 125 °C, unless otherwise noted. Typical values are characterized at VIN = 5 V and TA = 25 °C unless otherwise noted. Symbol Description Min Typ Max Unit tBias System bias turn-on time • From wake-up event (PWRON or cold boot) • Analog core biasing until digital supply is in regulation. – 370 625 µs tFLoad Fuse load time • VDIG in regulation to FUSE_LOAD_DONE – 190 200 µs tSTEST Self-test time • From PWRON event detected until STEST_DONE • PWRUP_READY = STEST_DONE, assuming no event is gating the power-up sequence. – 770 800 µs tLBIST LBIST test time • LBIST enabled • Includes initial fuse load – – 4.5 ms tFirst Time from PWRUP_READY to regulator in first slot to start rising. – – 100 µs Table 27. IC startup dynamic characteristics PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 1.3 — 16 December 2025 Document feedback 33 / 205 |
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