MPF0900AMBA2ES datasheet(69/205 Pages) NXP

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NXP Semiconductors

PF09

Nine-channel power management IC with advanced system safety monitoring

TRESET[1:0]

Time to reset

2 sec

8 sec

16 sec

Table 65. Time to reset...continued

In the edge-sensitive mode, The PF09 uses the PWRON_DBNC[1:0] bits to set the PWRON pin debounce on

the rising and Falling edges.

PWRON_DBNC[1:0]

Falling-edge debounce

Rising-edge debounce

32 ms

125 ms

32 ms

750 ms

32 ms

Table 66. PWRON pin debounce

The OTP_PWRON_DBNC[1:0] bits are used to set the default debounce time for the PWRON pin upon a power

up.

The PWRON_1S_I, PWRON_2S_I, PWRON_3S_I, PWRON_4S_I and PWRON_8S_I interrupts are generated

when the PWRON pin is held low for longer than 1 s, 2 s, 3 s, 4 s and 8 s respectively.

If PWRON_RST_EN = 1, pressing the PWRON for longer than the delay programmed by OTP_TRESET[1:0]

will force a PMIC reset.

If PWRON_RST_EN = 0, the device will start a turnoff event after the pushbutton is pressed for longer than

TRESET[1:0].

12.8.3 STBY

When the STBY pin is asserted, the device is directed to enter the STANDBY state, and when de-asserted, it

will return to the RUN state.

The STBY pin is programmable as active-high or active-low using the STBY_POL bit.

STBY (pin)

STBY_POL

STANDBY control

Not in STANDBY mode

In STANDBY mode

Not in STANDBY mode

Table 67. STBY pin polarity

The OTP_STBY_POL bit is provided to set the default value of the STBY_POL bit.

The PF09 features a selectable STANDBY request window to allow the system to safely move into the

STANDBY state when the STBY pin is toggled, and to prevent random access to the STANDBY state.

To exit the STANDBY state, the device requires only the STBY pin toggle in the corresponding state, without the

need for any STANDBY request command.

The OTP_STBY_REQ bit is provided to configure the operation of the STANDBY request window.

PF09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 16 December 2025

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