MPF0900AMBA2ES datasheet(59/205 Pages) NXP

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NXP Semiconductors

PF09

Nine-channel power management IC with advanced system safety monitoring

12.7 System diagnostics

12.7.1 System fault flags

The PF09 provides dedicated flags to improve the system diagnostics when fault, reset or turn-off conditions

have been detected.

System diagnostic flags can be cleared manually by writing a 1 to the corresponding bit, and the values of the

flags will remain unchanged as long as the digital supply (VDIG) does not cross the internal POR threshold. The

following scenarios will cause a loss of the internal VDIG, hence a loss of the system fault flag:

• VIN goes below the VIN_POR threshold

• The device is in the ULPOFF state.

• VDIG supply is shorted externally (fault condition)

Table 56 provides a summary of the system diagnostic faults available in the PF09 devices.

Diagnostic flag

Description

DCRC_FLG

Flag is set when a dynamic CRC error is present

DFS_FLG

Flag is set when device is waking up from the DFS state

VIN_OV_FLG

Flag is set when a VIN_OV condition is present

XFAIL_FLG

Flag is set when a power-down event was initiated via the XFAILB pin.

WD_FLG

Flag is set when a watchdog reset event is initiated.

XRESET_FLG

Flag is set when an external reset is requested via the XRESET or FCCU blocks

SFAULT_FLG

Flag is set when a soft fault is present (OV/UV/ILIM)

HFAULT_FLG

Flag is set when a hard fault is present.

Table 56. System diagnostic flags

The hard-fault event has dedicated flags to trace the source of failure.

Hard-fault Flag

Description

UVDET_FAIL

This flag is set automatically when the device crosses the UVDET threshold in the rising

edge, to indicate the device is waking up from the DFS state after a VIN < UVDET condition.

RSTB_FAIL

The RSTB is externally held low for longer than the OTP_RSTB_TSHORT[1:0]

PU_FAIL

A power-up failure started the hard fault.

RESET_FAIL

The Reset counter reaches the maximum number of events allowed. (RESET_CNT[3:0] =

RESET_MAX[3:0])

FLTCNT_FAIL

The Fault counter reaches the maximum number of failures allowed. (FAULT_CNT[3:0] =

FAULT_MAX_CNT)

REG_FAIL

A fault condition in a regulator causes a hard fault. (Fault timer, VAON UV not

acknowledged)

TSD_FAIL

A power-down sequence is initiated due to a thermal shutdown event.

Table 57. Hard-fault Flags

The MCU is able to read the fault flags during the system-on states in order to obtain information about the

previous failure, provided the state machine is able to power up successfully after such a failure.

PF09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 16 December 2025

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