MPF0900AMBA2ES datasheet(75/205 Pages) NXP

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NXP Semiconductors

PF09

Nine-channel power management IC with advanced system safety monitoring

OTP_FCCU0_MODE[1:0]

OTP_FCCU1_MODE[1:0]

FCCU1 Operation

Don’t care

No operation

Don’t care

No operation

Don’t care

XRESET enabled

Table 75. FCCU1 pin operation when FCCU block is not available in the system....continued

In devices where the FCCU operation is available, the FCCU1 pin operation is set based on the

OTP_FCCU1_MODE[1:0] and OTP_FCCU0_MODE[1:0] bits.

OTP_FCCU0_MODE[1:0]

OTP_FCCU1_MODE[1:0]

FCCU1 Operation

00, 01, 10

No operation

00, 01, 10

FCCU1 single-ended Level detection[1]

00, 01, 10

FCCU1 single-ended PWM detection[1]

00, 01, 10

XRESET enabled

00, 01[2]

FCCU bi-stable[1]

Hybrid mode (XRESET / FCCU bi-stable) [1]

Table 76. FCCU1 pin operation when FCCU block is available in the system.

[1]

For a detailed description of the FCCU operation, refer to section 18.7 FCCU Monitoring.

[2]

Code 10 in the OTP_FCCU1_MODE[1:0] shall not be used when the FCCU Bistable mode is selected.

When the XRESET is enabled, the FCCU1 pin operates as an external reset input (XRESET). When the input

is asserted, the device will generate a reset event to place the PMIC in a default known state. Refer to section

16.4.2 Reset Conditions for a detailed description of the implementation of a reset condition.

The polarity to detect a reset condition on the XRESET input is configured using the FCCU1_POL bit.

FCCU1_POL

XRESET polarity

Reset event on rising edge

Reset event on Falling edge

Table 77. XRESET polarity

The OTP_FCCU1_POL bit is provided to set the default value for the FCCU1_POL at power-up.

The XRST_DBNC[1:0] bits are provided to program the debounce filter to detect an external reset event on

either the rising or Falling edge of the XRESET input.

XRST_DBNC[1:0]

XRESET debounce timer

10 μs

50 μs

500 μs

1000 μs

Table 78. XRESET debounce timer

The OTP_XRST_DBNC[1:0] bits are provided to set the default value for the XRST_DBNC[1:0] bits at power-

up.

The XRST_MODE bit is provided to set the reset type generated upon an XRESET event.

PF09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 16 December 2025

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