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MPF0900AMBA2ES датащи(PDF) 28 Page - NXP Semiconductors

номер детали MPF0900AMBA2ES
подробное описание детали  Nine-channel power management IC with advanced system safety monitoring
PDF  205 Pages
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производитель  NXP [NXP Semiconductors]
домашняя страница  http://www.nxp.com
Logo NXP - NXP Semiconductors

MPF0900AMBA2ES датащи(HTML) 28 Page - NXP Semiconductors

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NXP Semiconductors
PF09
Nine-channel power management IC with advanced system safety monitoring
12 General device operation
12.1 UVDET
VIN > UVDET is a mandatory condition for the PMIC to start a power-on cycle. Once a power-on cycle is
started, the device allows full operation as long as VIN does not fall below the falling UVDET threshold.
When VIN falls below the UVDET threshold in any state after the DBGOFF state, the device moves to the Deep
Fail-safe state and waits for proper conditions to exit the DFS state.
When the VIN crosses the UVDET threshold on the rising edge, the devices will set the UVDET_FAIL flag to 1
to provide debugging information to the system. The UVDET_FAIL bit can be cleared by writing a 1 to it.
All parameters are specified at TA = -40 °C to 125 °C, unless otherwise noted. Typical values are characterized at TA = 25
°C, unless otherwise noted.
Symbol
Description
Min
Typ
Max
Unit
VUVDET_RISE
Rising UVDET
2.8
2.85
2.9
V
VUVDET_FALL
Falling UVDET
2.7
2.75
2.8
V
Table 22. UVDET electrical characteristics
12.2 VIN OV monitoring
The VIN_OV monitor is provided as a last-resort protection against a VIN supply out of range, and its main
purpose is to prevent PMIC operation with a VIN condition out of the maximum operating range of the PF09.
The VIN_OV monitoring can be enabled or disabled by default in the OTP registers via the OTP_VIN_OV_EN
bit, and the function can be disabled during the system-on states for system debugging purposes via the
VIN_OV_EN functional bit.
VIN_OV_EN
VIN OV monitor
0
Disabled
1
Enabled
Table 23. VIN_OV_EN bit
When the VIN_OV monitor is enabled, The device monitors its input voltage and is can be programmed to react
to an over-voltage as defined by the VIN_OV_SDWN bit. The default value of the VIN_OV_SDWN bit is set in
the OTP registers via the OTP_VIN_OV_SDWN bit.
VIN_OV_SDWN
VIN OV reaction
0
Interrupt Only
1
PMIC Shutdown
Table 24. VIN_OV_SDWN bit
The VIN_OV is available during the monitored system-on states (RUN and STANDBY) and also during a power-
up event to ensure the system is not started with a VIN fault condition present.
If a VIN_OV condition is present during a power-up event, the device will not allow the power-up sequence to
start, regardless of the value of the VIN_OV_SDWN, to prevent the system from starting with a potential fault
condition.
PF09
All information provided in this document is subject to legal disclaimers.
© 2026 NXP B.V. All rights reserved.
Product data sheet
Rev. 1.3 — 16 December 2025
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