MPF0900AMBA2ES datasheet(37/205 Pages) NXP

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NXP Semiconductors

PF09

Nine-channel power management IC with advanced system safety monitoring

aaa-056050

SW1

LDO1

SW3

RSTB

SW2

GPOx

INTB

SYSTEM ON

End of

PWRUP

Start of

PWRDN

Power-down seq.

Run to off

Power-up seq.

OFF to RUN

End of

PWRDN

Figure 11. Power up/down Transitions

12.3.3.2 Dynamic power-up

When the OTP_SEQ_MODE = 1, the device will power up in dynamic mode.

When operating in dynamic mode, the device uses the OTP_XXX_SEQ[7:0] bits to set the order in which the

system regulators will be enabled during the power-up sequence. The particular slot selection is not relevant

for the power-up sequence, instead, the slot number is used to create a hierarchical order during power-up.

(Regulators with lower slot numbers belong to a lower hierarchical level).

When the OTP_SEQ_MODE = 1, the power-down sequence still uses the XXX_SEQ[7:0] and TBASE[1:0] bits

to power down in the reverse time-based sequence as defined in Section 12.4.

Channel

OTP_XXX_SEQ[7:0]

Sequenced power

up/down slot

Dynamic hierarchical level

SW1

0000_0010

Slot 1

Level 2

SW2

0000_0100

Slot 3

Level 3

SW3

0000_1000

Slot 7

Level 5

SW4

0000_0111

Slot 6

Level 4

SW5

0000_0011

Slot 3

Level 3

GPIO1

0000_1000

Slot 7

Level 5

LDO1

0000_0010

Slot 1

Level 2

LDO2

0000_0000

OFF

VAON

0000_0001

Slot 0

Level 1

RSTB

0001_1111

Slot 31

Level 7

Table 31. Dynamic power down sequence example

Regulators with the lower hierarchical level power up first, and regulators in the next hierarchical level will start

powering up only after the previous regulators have reached the point of regulation.

PF09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 16 December 2025

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