MPF0900AMBA2ES datasheet(20/205 Pages) NXP

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NXP Semiconductors

PF09

Nine-channel power management IC with advanced system safety monitoring

In systems requiring to operate the PWRON pin in edge sensitive mode, the LPOFF state becomes the static

low-power state for the system, since the PWRON pin is expected to be pulled up to VIN externally. In this

scenario, the device will automatically detect a wake-up event upon entering the ULPOFF state, and proceed

to perform the fuse load routine and move into the LPOFF state to wait for a Falling edge on the PWRON pin to

generate a valid power-on event.

11.2.4 DBGOFF state

During normal system operation, the DBGOFF (debug off) state will be a transitory state between a power-on

event and the power-up sequence. It serves as the gating state to ensure the PMIC is ready to start a power-

up sequence, and allow synchronization of two or more PMICs providing full power architecture to a complex

system.

If the VDDIO supply is provided externally, the device is able to communicate through the I2C bus during

the DBGOFF state, allowing the PMIC to operate in development/debugging modes. In such scenarios, the

DBGOFF state becomes a full-biased OFF state, to allow full access to the functional and OTP registers to

enable OTP emulation and/or OTP fuse programming. Contact your NXP representative for detailed instructions

on OTP emulation and fuse programming.

If the VAON is set as an always-on Regulator, the VAON supply is monitored for OV/UV conditions to ensure the

supply is in regulation before allowing the power-up sequence to start.

If the XFAILB synchronization function is available, the device will use the DBGOFF state as the

synchronization point to start the power-up sequence. The PF09 will release the XFAILB pin internally when it is

ready to start the Power-up sequence, based on the following conditions:

• Self-test has finished (if self-test is available in the device)

• && The LBIST_STATUS[1:0] is different from 0b10 (if LBIST is available in the device)

• && the fuse loading (_NOK - Register Address Flags: 0x2D) flags are not asserted

• && VAON has reached regulation (if VAON set as always-on regulator)

• && VIN < VIN_OV (if the VIN_OV monitor is enabled)

• && TJ is at least 10 °C below the TSD threshold

• && VDDOTP < 3.0 V

If any of the conditions mentioned above are not met, the XFAILB will remain asserted and the device will

remain in the DBGOFF state until all conditions are met. Once the XFAILB pin has been internally released, the

device will monitor the XFAILB pin to pause the power-up sequence until the pin has been released HIGH by all

devices connected to it.

If the XFAILB synchronization function is not available, the XFAILB status is no longer a condition to proceed

with the power-up sequence and the following conditions must be met to allow the power-up sequence to be

started:

• Self-test has finished (if self-test is available in the device)

• && The LBIST_STATUS[1:0] is different from 0b10 (if LBIST is available in the device)

• && the fuse loading (_NOK - Register Address Flags: 0x2D) flags are not asserted

• && VAON has reached regulation (if VAON set as an always-on regulator)

• && VIN < VIN_OV (if VIN_OV monitor is enabled)

• && TJ is at least 10 °C below the TSD threshold

• && VDDOTP < 3.0 V

In the event the device is stuck in the DBGOFF state, a power-off event in the PWRON pin will send the device

to the corresponding OFF state and wait for a new power-up event to attempt the power-up sequence again.

PF09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 16 December 2025

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