MPF0900AMBA2ES datasheet(93/205 Pages) NXP

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NXP Semiconductors

PF09

Nine-channel power management IC with advanced system safety monitoring

13.2.2 SW1 (3.5 A peak/valley current mode buck regulator)

The PF09 features one low-voltage peak current mode (PCM) or valley current mode (VCM) buck regulator with

wide output voltage range from 0.5 V to 3.3 V, with up to 1.5 % output accuracy and 3.5 A nominal load current

capability.

The default voltage configuration for the SW1 regulator at power-up is set in OTP via the OTP_VSW1_RUN[7:0]

bits, and the dynamic configuration of the output voltage during the RUN state is controlled via the

VSW1_RUN[7:0] functional bits.

The default voltage configuration for the SW1 regulator to be used during the STANDBY state is set in OTP

via the OTP_VSW1_STBY[7:0] bits, and the MCU can modify the target STANDBY voltage configuration of the

SW1 regulator during any of the SYSTEM ON states via the VSW1_STBY[7:0] functional bits.

The MCU is expected to update the VSW1_STBY[7:0] bits before directing the PMIC to enter the STANDBY

state. The selection of the VSW1_STBY[7:0] will depend on the system requirements of the specific low-power

mode it wants to achieve at the system level.

VSW1_RUN[7:0] VSW1_STBY[7:0]

Voltage setting

0x00 to 0x08

Reserved

0x09 to 0x91

0.50000 V to 1.35000 V in 6.25 mV steps

0x92 to 0x9E

Reserved

0x9F

1.50000 V

0xA0 to 0xD8

1.80000 V to 2.50000 V in 12.5 mV steps

0xD9 to 0xDF

Reserved

0xE0 to 0xF4

2.80000 V to 3.30000 V in 25.0 mV steps

0xF5 to 0xFF

Reserved

Table 110. SW1 output voltage configuration bits

DVS is available under the following conditions:

1. Dynamic voltage scaling (DVS) range is between 0.65 V and 0.9 V.

2. The OV/UV threshold is +/-5% or wider.

3. DVS ramp must be 3.9 mV/μs or slower.

The VSW1_RUN[7:0] and VSW1_STBY[7:0] bits are implemented as secure write bits to ensure that the output

voltages are not changed by mistake during the SYSTEM ON states.

The OTP_SW1_DVS[1:0] bits are used to program the default slew rate for the SW1 turn-on and turn-off ramps.

During the SYSTEM ON states, the DVS rate can be changed dynamically to allow different voltage scaling

slew rates as required by the system. The SYSTEM ON DVS rate is controlled by the SW1_DVS[1:0] bits on the

functional registers.

SW1_DVS[1:0]

Clocking factor

SW1 ramp-up slope rate [1][2]

SW1 ramp-down

slope rate[1][2]

1.95 mV/µs

3.9 mV/µs

7.8 mV/µs

15.6 mV/µs

Table 111. DVS ramp selection bits

[1]

At 20 MHz high frequency clock selection.

PF09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 16 December 2025

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