MPF0900AMBA2ES datasheet(97/205 Pages) NXP

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NXP Semiconductors

PF09

Nine-channel power management IC with advanced system safety monitoring

scenarios, the SW1 block can be used as a low-drop load switch to enable the 3.3 V input to be switched on

and off as required by the system.

The OTP_SW1LS_EN bit is provided to configure the SW1 block as a load awitch (SW1LS). In this mode of

operation, no inductor is required, and the SW1LX pin is used as the output of the load switch, which must be

connected to the SW1FB pin to monitor the output voltage.

When the SW1LS output is disabled, the internal HS FET becomes open and the internal pulldown is applied to

discharge the output.

OTP_SW1LS_EN

SW1 mode

Regulator mode

Load switch mode

Table 120. Load switch mode selection bit

The SW1 load switch (SW1LS) is intended to take a 3.3 V input and gate the output using the

SW1_RUN_MODE[1:0] and SW1_STBY_MODE[1:0] in the RUN and STANDBY states respectively.

SW1_RUN_MODE[1:0] SW1_STBY_MODE[1:0]

SW1LS Operation

Output disable (HS FET open)

Output enabled (without monitoring)

Output enabled (with monitoring)

Reserved (output disabled)

Table 121. SW1LS control bits

When the SW1LS output is enabled during the Power-up sequence, the SW1_RUN_MODE[1:0] will default

to 0b10 (output enabled with monitoring). The system can change the configuration during the SYSTEM ON

states.

The default value of the SW1_STBY_MODE[1:0] at power up is set based on the OTP_SW1_STBY_EN[1:0]

and the OTP_LP_STBY bits.

OTP_SW1_STBY_EN

OTP_LP_STBY

SW1_STBY_MODE[1:0]

Default STANDBY operation

Output disable (HS FET open)

Output enabled with monitoring

Output enabled no monitoring

Table 122. SW1LS default STANDBY configuration

When the SW1LS output is enabled with no monitoring, the SW1 output will neither control the PGOOD pin nor

generate an OV/UV condition.

When the SW1LS output is enabled with monitoring during the RUN state, the internal voltage monitor will be

enabled and will expect a voltage as selected by the VSW1_RUN[7:0] bits.

When the SW1LS output is enabled with monitoring during the monitored STANDBY state, (OTP_LP_STBY =

0), the internal voltage monitor will be enabled and will expect a voltage as selected by the VSW1_STBY[7:0]

bits.

When the internal monitor is expected to be enabled during the load switch operation, the system designer must

ensure that the output voltage in the corresponding state is always set to 3.3 V or a lower value, and the OV/UV

monitoring thresholds are wide enough to account for voltage losses in the load switch.

PF09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 16 December 2025

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